synchronize loops in FPGA VI

[duraik756]

Hi 

    I have PXIe_1095,PXIe_8881 18 core embedded controller and PXIe 6569 modules. PXIe -6569 configured as 32 Tx and 32 Rx channels. i have implemented serdes clip in project using examples (PXie6569-Serdes (KU060).so the nodes of write and read will be u8 data type in FPGA VI(clock rate will b e 10Mhz to 156.26Mhz) .I am trying to transfer u8 data in tx channel and read same data in Rx channel in FPGA VI. The Tx node and RX node will be in separate loops. unfortunately i could not get same data. i have to calculate bit error rate. how to synchronize two loops in FPGA VI

[ZYOng]

Usually we place all the items we want to synchronize inside the same loop.

See FPGA Interprocess Communication for different data transfer options between loops.

[duraik756]

Hi ZYOng

Thanks for reply.i am using seperates nodes for node because i am using serdes CLIP.