test FXP LMS fpga

[charansai]

 So, I generated FXP LMS algorithm as quoted below.

'' Right-click an FPGA target in the Project Explorer window and select Start IP Generatorfrom the shortcut menu to display the Start IP Generator dialog box. Select LMS Adaptive Filters and click the OK button in the Start IP Generator dialog box to display the Generate LabVIEW FPGA Code for LMS Adaptive Filter dialog box. '' 

Quoting from [http://zone.ni.com/reference/en-XX/help/372357A-01/lvaft/aft_db_codegen/]  .

 I might can not call this algorithm as IP Generated Algorithm, I don't know ! The Xilinx IP generated FIR Filters that you are talking about , I don't have any idea as what they are, and how they are generated. It would be really interesting to know about them 🙂

FXP LMS.vi please check below ! 

[Maxe93]

Hello charansai,

sorry for the late response but the problem isn't trivial.

Now we tried to use DMA FIFOs that each iteration a new value is written to the filter and sends the filter's output to a DMA FIFO up to the host VI.

Attached you can find my project and the result of the FPGA Code.

Open the project 'Eigener Test2.lvproj'.

You can see that once you pass new values and read a single output each iteration you see more expected behavior from the filter.

The result is still different to the RT-Code's result but now as long as we properly run this FPGA VI we see a valid output (not all 0's).

I hope that will help you.

Regards, 

Maxi