LabVIEW
the problem running
Yes, you should save everything as LabVIEW 7.1 version before running. Your main VI is OK, but the subVIs should also be converted AND saved.
I cannot tell if there are any more serious problems because I cannot run your VI. Why don't you implement the simple changes described in my previous message and see if things have improved? If not, we can study it further.
Later, there are many other minor things that can be improved, but I don't think they are directly related to your memory problem. For example you could open the lower file once at the beginning and keep it open during the entire run. This would probably be more efficient than constantly opening and closing the same file. Overall, the entire diagram could be cleaned up a bit to make it easier to read, e.g. keep the two file I/O threads aligned horizontally. Make the hidden wires visible, e.g. the boolean input for one of the case structures is hidden. USe path constants instead of string paths to make the program platform independent. I have also no idea about the purpose of all these back-and-forth formatting and conversion steps in the big case structure. There has to be a simpler way! Can you explain why you do it like this and what it is supposed to do?
The attached VI has the code arrranged so it is easier to follow the code. (I have not implemented many of the suggested code changes from this message!) All wires are now visible, flow left to right, and related process threads are arranged horizontally.
I cannot tell if there are any more serious problems because I cannot run your VI. Why don't you implement the simple changes described in my previous message and see if things have improved? If not, we can study it further.
Later, there are many other minor things that can be improved, but I don't think they are directly related to your memory problem. For example you could open the lower file once at the beginning and keep it open during the entire run. This would probably be more efficient than constantly opening and closing the same file. Overall, the entire diagram could be cleaned up a bit to make it easier to read, e.g. keep the two file I/O threads aligned horizontally. Make the hidden wires visible, e.g. the boolean input for one of the case structures is hidden. USe path constants instead of string paths to make the program platform independent. I have also no idea about the purpose of all these back-and-forth formatting and conversion steps in the big case structure. There has to be a simpler way! Can you explain why you do it like this and what it is supposed to do?
The attached VI has the code arrranged so it is easier to follow the code. (I have not implemented many of the suggested code changes from this message!) All wires are now visible, flow left to right, and related process threads are arranged horizontally.
Good point. There is a 2s wait in the outer true case on the left, but studying this a bit further shows that this case occurs only rarely (~every hour?), so there is definitely a need for a wait unless e.g. the serial communication provides some pacing, something that I cannot test.
I am still curious for an explanation of that 8 item sequence to simply get a DBL out of a string... 😉
I am still curious for an explanation of that 8 item sequence to simply get a DBL out of a string... 😉
