time delay feedback

[bobdone]

HI James,

Thanks for the help. So the FPGA PCI card will definitely allow me to carry out what I showed in that PNG figure I posted (most importantly capturing by AI, storing, shifting and then outputting to AO waveforms with us precision while simultaneously runnning another AO and AI)? I'm afraid I don't have any experience programming FPGA and very limited experience overall with labview. My Labview code isn't that complicated.

 Cheers,

Steve

[srm@viewpointusa.com]

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bobdone wrote:

HI James,

Thanks for the help. So the FPGA PCI card will definitely allow me to carry out what I showed in that PNG figure I posted (most importantly capturing by AI, storing, shifting and then outputting to AO waveforms with us precision while simultaneously runnning another AO and AI)? I'm afraid I don't have any experience programming FPGA and very limited experience overall with labview. My Labview code isn't that complicated.

 Cheers,

Steve

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Yes the FPGA will do what you describe.  I will update the example I posted to do what you describe.  The only fuzzy part I am concerned with is the recording to disk.  What rate are you looking to store to disk?  I would have to test to see if there are going to be issues with acquiring at full rate (~833 KHz).

Stu

[Ben]

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stu@viewpointusa.com wrote:

....  The only fuzzy part I am concerned with is the recording to disk.  What rate are you looking to store to disk?  I would have to test to see if there are going to be issues with acquiring at full rate (~833 KHz).

Stu

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Stu,

A trick form the "old days" is to just use anther system to do the recording.

Yes there are more elegant ways that require less hardware.

Ben

[srm@viewpointusa.com]

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bobdone wrote:

HI James,

Thanks for the help. So the FPGA PCI card will definitely allow me to carry out what I showed in that PNG figure I posted (most importantly capturing by AI, storing, shifting and then outputting to AO waveforms with us precision while simultaneously runnning another AO and AI)? I'm afraid I don't have any experience programming FPGA and very limited experience overall with labview. My Labview code isn't that complicated.

 Cheers,

Steve

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See attached code.  FPGA code to perform the algorithm you describe.  This is coded for minimum delay.  longer delays are obviously possible.