timing violation Labview FPGA

[crossrulz]

Directly on the cRIO chassis?  Not one of the expansion chassis?

I'd start by getting rid of those variables from your system.  Use a DMA to pass your data up to your RT system.

You also have nothing to time the loop.  You likely want to put in a loop timer.

But 10ms is an eternity for an FPGA.  Why can't you just use the Scan Engine and do any calculations you need to in the RT?

[AFLAMENT]

Yes directly on the chassis

(getting rib? my english is bad)

Ok I should use a timed loop, timed with de 40Mhz clock??

Did I need to use start end stop module?

I use also a RT vi who use data from FPGA

[crossrulz]

I am recommending not using the FPGA at all.  Use the cRIO Scan Engine instead.  You are sampling so slowly that it makes no sense to do the work in the FPGA when NI can do it all for you very easily.