on my fpga vi, i have two while loops running in parallel. one while loop generates an interrupt with IRQ=0 to the host every 10sec. the other while loop generates an interrupt with IRQ=1 to the host every 5sec. on the host side, two seperate subvi's running in parallel are waiting for interrupts from one of the two IRQ lines. somehow it seems like that everything works fine if i disable one of the two IRQ interrupts, but when both are enabled, neither one can be picked up by the host consistently.
what will be a general optimal strategy to deal with this issue? i would like to avoid polling if possible.