varying the rise time and fall time of CLK

[ananthi_g]

Hi all,

I need to vary the rise time and fall time of a clk signal to test my device. I am using LabVIEW FPGA to generate the clock signal. Can any one tell me how to do this?

Thanks,

Ananthi

[Karthikeyan_Mathiyalagan]

http://decibel.ni.com/content/docs/DOC-11079

Try this........