version control # fpga

[JFTICH]

This may be a simple question here for the LabVIEW FPGA gurus, or not possible right now....

Background:

I run a compile for my FPGA code with the latest tweak. I go to deliver it to the customer, only to realize I failed to change version control #. I keep a 32 bit number that allows the customer to see what the complie version is, to supplement them having to track it in their source code system

Right now, I recompile the whole thing after updating the version control #.

Actual question:

Is it possible to modularize this somehow? Or is there a means to not have to recompile the whole bitstream?

Thanks in advance...

[Xaq]

JFTICH-

Are you storing this 32Bit # inside of the VI (like in a constant)? If so, then you will have to recompile after each time you change it, unfortunately. It might be easier to keep the vesion number in the host VI instead of the FPGA VI, which would save you from having to recompile.

Xaq

[Xaq]

I almost forgot....


You can also keep the version number in the Documentation section of the VI Property, saving you from recompiling.


Xaq