08-15-2008 09:51 AM
When analysing a VI, The VI analyser report some error about nodes in the VI and report broken arrow in FPGA VI. So Does it any way to make VI analyser to recognise FPGA target?
B.
08-18-2008 05:58 AM
08-18-2008 07:17 AM
Read my question...????!!!!! I said it in....
B.
08-18-2008 07:30 AM
08-18-2008 05:46 PM
Hi Benoit,
I believe I understand what you saying. Unfortunately the VI Analyzer Toolkit is not able to successfully analyze FPGA or Real-Time VIs at this time. You be will able to run the analysis on the VIs, but the results will not be entirely appropriate. You will also see FPGA or Real-Time specific portions of your block digram "break" since the analyzer takes the VI out of the context of the project.
So, no , there is not a way to make VI analyzer recognize an FPGA target. I am sorry if this response isn't what you are looking for!
Regards,
08-19-2008 07:48 AM
Effectively, It's not the answer that I want. But I prefer knowing that it's not possible than thinking that I'm doing something wrong.
Thanks.
B.