vi not in memory real-time

[craige]

I've been working a lot with Compact RIO (LabVIEW 8.2.1) over the past year and have often come across the following error in the Deployment Window when attempting to load a Real-Time which calls an FPGA VI by reference to my controller.

All supporting VIs load successfully but the final VI (my RT Host VI) produces this error:

"VI not found in memory"

I have tried a combination of reboots and resets with no success. Also, I find I am able to load simple Real-Time application which does not call an FPGA VI. I can even load a Real-Time and FPGA example from the examples LabVIEW provides and it runs correctly. The only solution that seems to work is recompiling my FPGA VI and relinking this to my Open FPGA VI Reference contained within my Real-Time VI. Seems like the FPGA/Xilinx compiler is flaky. Yes?

Has anyone else experienced this problem? Is there a workaround or action I should be avoiding? It does not appear to be a commonly Known Issue

Thanks,

Craig

Message Edited by craige on 08-30-2007 10:05 AM

[Coal_Man]

Hi Craig,

Is this something that just happens intermittently or all the time?  If it's all the time, then it may be easier to track down.

Also, does the error happen on deployment, or when the RT VI is run?  It could be that the FPGA bitfile is not being downloaded when you deploy the RT host VI.  Thus the VI would not be found in memory, since the bitfile is not on the FPGA, and the host VI would error out. 

Can you post the code that you were using to deploy to the cRIO system?  I am curious to try to replicate this problem.  Also, what chassis and controller are you using?

Finally, what happens when you just update the Open FPGA Reference VI on the host?  Does it require a recompile?  Can you point it to the bitfile instead of the VI itself?

I would try relinking the Open FPGA Reference to the VI, and going from there.  I think it is either a problem that the PC doing the deploying can't see the FPGA VI, or the RT host VI cannot find the FPGA bitfile on the FPGA. 

[craige]

A year later and I'm doing some house keeping......just ran into my old post. I'll do my best to answer the questions as I recall just in case others might find this information useful: 

This error actually happened while I was taking the CRIO course at NI in Austin some time ago. I tried almost everything from switching hardware (new controller and chassis) to switching computers. In the end it seemed to be a problem with the relationship between my RT HostVI, my FPGA VI, and my bitfile.

This was an issue that happened intermittantly. Seems like if the FPGA was ever saved that LabVIEW would recognize the file needed to be recompiled. Perhaps I edited the FPGA VI from outside the project causing this notification to never occur. That would make the most since to me.

The error occured when the RT VI was run and when it was attempted to be deployed. I believe I tried running the FPGA VI with an active front panel and it even seemed to work fine.

I do not have the code any more but I'm about to start up on a new CRIO project (probably in 8.6 though) but perhaps I will have some time to dabble in my old code.

When I updated the bitfile on the RT application (host) the VI did not complain. I attempted linking to the bitfile directly and the RT host vi still did not complain. Only when I deployed or attempted to run did this issue occur.

The best solution was to recompile the FPGA. Luckily in this case it only took 20mins or so. The issue seems to have to do with LabVIEW recognizing the link between the RT and the FPGA VI/Bitfile but linking to an old version and failing to tell me it needs to recompile to really run. In otherwords the VI and the bitfile (although seemingly the same version) have somehow not been updated in parallel so the VI requires a recompile even though LabVIEW doesn't complain about it.

I'll update more if I end up playing around or teaching a CRIO class to someone.

Craig

Message Edited by craige on 10-06-2008 05:51 PM