warning: connection to the target (cRIO)has been lost

[uma0732]

When iam running this particular VI attached below, the cRIO automatically gets disconnected after running for couple of seconds and showing the warning  " connection to the cRIO has been lost ".Then for second time i have to reconnect the cRIO and then deploying the program .

Can anyone find the reason for it,i already checked for the possible reasons discussed in forum, i couldn't find out still.please help with this.

[deceased]

I cannot look at the VIs right now, but do other VIs run OK without disconnection? I want to help rule out other problems.

Look for any greedy loops (with no delays) that might abuse the CPU and starve out the background comms routines.

Also it may be useful to say which version of LV you use (for example LVRT2010 has a bug that causes repeated disconnects if NI Timesync is installed). I have felt its pain before.

[uma0732]

Dear sir,

other VI's run continuously.Even when i run the Analog Input VI in FPGA it is running properly.only when i run the calibration subvi it gets disconnected. I am using cRIO 9035 controller and Labview '16 is installed both in cRIO and computer.

[uma0732]

iam attaching the screen shot of calibration subVI, only one loop is shown in screen shot,similarly 3 while loops capturing data from 2 different modules NI 9215,NI 9219 is done.

[GerdW]

Hi uma,

are you trying to start a FPGA vi in three loops in parallel? Are you trying to start that FPGA vi with each iteration of those loops?

Common usage is to start one (1) FPGA vi before any loop, then access it's controls/indicators in those loops…

[uma0732]

Dear sir,

i want to run all the three loops parallel to acquire continuous data from FPGA VI.This is the first time iam using FPGA .Can u please tell me how to start the FPGA VI common for it.

i tried by running the FPGA vi first and then the calibration subvi is run,afterwards it gets disconnected.Also want to know that the way iam running all the three loops parallel is right or wrong?

[GerdW · Accepted solution]

Hi uma,

running those loops in parallel is no problem, I do this all the time.

BUT: you need to open&run the FPGA VI once before those loops, then just wire the same FPGA reference to the loops. (And of course you only need to stop this FPGA vi just once after the loops have finished…)

[uma0732]

Dear sir,

Thanks for the solution ,it solved the problem.

attached the screen shot. i opened and run the FPGA before the loop.

thanks for everyone who helped me to solve the problem.

[GerdW]

Hi uma,

according to your text you are calling FPGAOpen and the Run invoke node before the loop(s) - but your image shows different code…

[uma0732]

oops,i have attached the old screen shot wrongly.

sorry!

herewith iam attaching the corrected one.

thanks for pointing out.