09-30-2007 02:09 AM - edited 09-30-2007 02:09 AM
帖子被blacksmith在09-30-2007 02:11 AM时编辑过了
09-30-2007 02:32 AM
The wire creates an artificial data dependency. The wire ensures that the two while loops cannot start until the subVI on the left has finished executing. THis is the desired behavior.
Without that wire, the subVI and the two loops would all start at the same time (or at least in unpredictable order), possibly leading to unpredictable behavior. For example, it could happen that the "write" operation in the first loop would execute before the "empty" operation on the left.
09-30-2007 03:15 AM