why does a simple program utilize a lot of resource on PXIe 5170r ?

[meh1011]

Hi

I tried to set up the PXIe 5170r card with simple FPGA program ( a loop just with a counter), after compilation of the program i saw this simple program take 50% of total Slice, 34% LUT,  27% Block RAM , even though i just used a numeric constant with an adder in a single cycle loop. 

what's wrong??!!

thanks for your help 

[Norbert_B]

First and foremost: Why is this a concern?

While i no FPGA expert, you have to keep in mind several facts:

• LV code has to be converted to HDL before the Xilinx tools can work with it. While this conversion is often considered to be very well performed (including resource usage), the resulting HDL code is not the manual best optimized code. However, manual optimization takes a lot of time while carving out only little improvement
• AFAIK, Xilinx tools have a simple approach: Compile the HDL code as fast and simple as possible (so no resource optimization taking place!), if it fits, keep it, if not, start optimizing with iterative cycles of compilation
• If a single loop takes X amount of resources, it is simply not true to state that two identical loops will take the double amount (2X) of resources

I do recommend that you benchmark a use case which fits your worst case (read: most functionality) usage of the FPGA. If it does not fit, you can start optimizing FPGA code.

You might also be interested in this FPGA guide.

[meh1011]

5170r is equipped with a kintex7 FPGA that has 57000 slice as total resource. it's not acceptable that a simple counter utilize about 50% slice. 

[Terry_ALE]

I am with you on this and am in no way defending LabVIEW FPGA in this case.  Admittedly I am a fan of the tool.  Here is what I know:

1. There are non-diagram elements such as PXIe and FAM interfacing that get compiled into your design no matter how much or how little.  As an exercise try compiling an empty VI and observe the utilization.

2. The FPGA compile tool (Xilinx) will "try harder" the more your design fills up.  That is, try putting two or even three times he logic and I bet it will fit.  There are technical reasons why this is non-linear. See https://electronics.stackexchange.com/questions/183214/nonlinear-increase-in-logic-utilization-for-f... and http://forums.ni.com/t5/forums/v3_1/forumtopicpage/board-id/170/thread-id/141325