xilinx dds compiler v6.0

[feitianlaoteng]

I am using labview fpga to generate sin and cos signal. When I use xilinx ip core dds compiler v6.0, and choose the output is sin and cos, these two signal are combied into a 32-bit data, how can I seperate this data into two 16-bit signals in labview fpga module?

[carmen9]

Hi,

I think you can refer to this:

http://www.ni.com/en-us/innovations/white-papers/06/advanced-data-acquisition-techniques-with-ni-r-s...