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DMA FIFO - random values?

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iHi all,

 

Apologies if this is in the wrong board ... not sure where it should go! Just to state upfront, I can't share VIs due to IP issues etc ... sigh.

 

Basically I have an sbRio 9626 and software running on the FPGA to interface with external analogue-to-digital converters. This is done using a state machine (single cycle timed loop with a case structure inside so it transitions between cases each tick of the FPGA clock). Inside one of the cases (states) I have a little routine which takes data from an ADC and places it in a target-to-host DMA FIFO buffer. In fact, there are 4 DMA FIFO buffers sending various information along with the sample value. This is then read by software on the RT Host and processed to produce an array of values which I then send to the PC using a shared network variable.

 

What I wanted to check was that the data being sent from FPGA to RT Host (and to PC) is contiguous (i.e. I have my FIFO lengths right). I modified the FPGA code to use a counter instead of the sampled data so the FIFOs should simply send numbers in a sequence (1, 2, 3, 4, etc). I then examine that sequence to ensure it's correct and no data has been overwritten.

 

What I find is that FIFOs 2, 3, and 4 are fine. FIFO 1 sends data that is continuous but every now and then I seem to get a random glitch. This glitch does *not*  appear to be due to FIFO lengths but seems to be an error in the data transfer. For example, I'll get something like 1, 2, 3, x, 5, 6, 7, y with x and y seemingly random values. The positions of x and y in the sequence are also seemingly random - they don't occur at the same point each time. The code writing to FIFO 1 is *exactly* the same as the others - in fact, it's the same dataset being written.

 

Anyone seen anything like this before? I'm trying to determine whether it's due to the target to host FIFOs or some problem with the network shared variable. Any suggestions as to what I might check? It almost looks as though there's EMI spikes on the transfer ... not suggesting that's the case but it gives an idea of what I'm seeing. I'm using Labview 2013 and BIOS on the sbRio is up-to-date. I do have another sbRio which I will try later to see if the problem is specific to one particular board. 

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Accepted by topic author Jimbo76

It seems you've found the wrong path here: since you are dealing with FPGA programming, which is essentially performed woth LabVIEW you should post this question to the LabVIEW board or maybe to the LabVIEW Embedded board



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Doh .. yes ... only now you've point it out it says labwindows ... lol thanks

 

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