Divide by 2 with PCI-6602

[kirkm]

Hi all,

I'm programming a PCI-6602 in LabWindows/CVI V8.1.  I'm using ctr2 as a "divide-by n" to scale down the
sample clock generated on a PCI-6132.  Everything works well as long as the divider is greater than 3. 

When I call DAQmxCreateCOPulseChanTicks I get an error if either the Low_Ticks or High_Ticks arguments are less than 2.

Any ideas on how to get a divide-by 3 or divide-by 2 using the PCI-6602?

Thanks,
Kirk

[stilly32]

Hi Kirk,

The minimum number of ticks you can specify for low/high ticks is 2 - giving you a min divide down of 4. That limitation will always be there, but we can get around it with more hardware. For example, the 6132 has two counters. You could use one to generate a pulse train at a multiple of your AI sample rate (say times 8). You could use the other counter to divide that down (by 😎 to your desired sample rate. You could then use a counter on the 6602 to divide down the first counters rate by 16, so that the rate on the 6602 is now half of the rate of your AI sample rate. You could set this up for a divide by 3 as well.

Will this work for you? If not, why do you need to divide down that sample rate - what are you going to be using that signal for? There may be other ways around this, please post back if you have additional questions.

Thanks,

Andrew S

National Instruments 

[kirkm]

Hi,
Starting with a scaled up frequency is a very good idea, I didn't think of that.  It should work in this case.

What I'm doing is sampling 2 counter channels on the PCI-6602 at the same time as the 4 analog channels on the PCI-6132 are sampled.  The counters contain up/down position information which I need to have synchronized to the analog data samples from a resolver.

The reason I'm dividing down is because I can't seem to get the PCI-6602 to store samples up at the 2.5Mhz sample rate of the PCI-6132.  I can get up to about 1Mhz but not much more.  So I figure I can get away with 1 counter sample for every 2 or 3 analog samples.  Any ideas on speeding up the PCI-6602 sample rate?

I was wondering if the the large buffer memory on the PCI-6132 can be used for counter samples?  Maybe I could switch my counting to that card???

Thanks,
Kirk

[stilly32]

Hi Kirk,

The counters on the 6602 and the 6132 both have extremely small FIFO (2 samples) so a buffered counter task is going to be system dependant. 1 Mhz is on the high end of what I've seen for these cards, so using a divide down is going to be a solid option. 

Since the 6132 doesn't have a larger FIFO, I would stick with the 6602 - the TIO cards are generally faster for these operations.

Hope this helps,

Andrew S

[kirkm]

Hi,

The application I'm working on will eventually run in a new computer.  It is presently on a Dell Precision 390 with 2.0GHz pentium 4.  It'll be interesting to see if it does better on the new computer which is a Dell Precision 390 with Core 2 Duo 1.86GHz.

When I think about it I'm not sure if the DMA transfer rate really depends on the CPU speed.  Probably a combination of the motherboard hardware and the CPU because there probably is some code that has to manipulate the data to get it to the user buffer specified in the DAQmxReadCounterU32 (...) call.  Or is there a big buffer into which it is directly DMA'ed and then transferred after all the data has been collected?  I'm kind of just thinking out loud but if you have any insight it would be interesting to know.

Thanks again,

Kirk

[MickeyD]

Hi Kirk,

The DMA transfer only depens on CPU speed to the extent the PC must be fast enough to respond to the DMA interrupts when the data transfer is finished.  So your application that is taking advantage of the DMA transfer will be CPU dependent.  The actual speed of the transfer does not depend on the CPU, and is a property of your communication bus.  The data is transferred off the FIFO of the board into RAM, which is where DAQmxReadCounter reads it.  The DAQmx read buffer is a allocated space in RAM.  I think this all being said your program will perform better upon a faster PC, because the processor will more likely get the necessary operations done before the DMA transfer interrupt occurs.  Let us know if we can be of further help in looking at this issue.

Have a great day,

Michael D
Applications Engineering
National Instruments