I'm building a camera with a Camera Link interface. I'm using a NI PCI 1426 and a custom LabView app for my basic testing. The camera uses an FPGA for the controller and a test pattern generator is included to prove out the interface. I've created a camera file using the NI Camera File Generator, and things are mostly working. What's odd is that the first line of each image, aqcuired using IMAQ Snap.vi, has its pixels offset. In other words, if the test pattern is a simple column counter, each row should simply count up: 0 1 2 3 4 etc up to 1023 (where it rolls over). But the first row starts at 2 instead of 0. Since it's a two-tap camera I assume that for whatever reason the first pair of pixels is being skipped.
I've verified that the test pattern is, in fact, correct, using both Xilinx ChipScope inside the FPGA and a logic analyzer connected to the DS90CR287 Camera Link interface chip.
To further add to the weirdness, if I Grab a series of images (using IMAQ Grab Setup.vi followed by IMAQ Grab Acquire.vi in a loop), only the first image in the series skips the first pixel. All other images are correct.
The help file for the Camera File Generator has a page about "Timing Signal Requirements." It's not made clear whether the requirements stated on that page apply to cameras with a parallel interface or to cameras with a Camera Link interface, or both. The requirements are:
- There must be at least four pixel clocks between lines and 100 pixel clocks between frames.
- There must be at least four Line Enable signals between frames. If the Line Enable signal does not meet this condition, you can use the Non Continuous Line Enable setting.
- The Line Enable and Frame Enable signals must be active for all valid pixels.
Presumably, "Line Enable" above refers to the Camera Link LVAL signal, and "Frame Enable" refers to the Camera Link FVAL signal.
Regarding the first requirement, I assume that this means that there must be at least four pixel clocks after the deassertion of the Camera Link LVAL signal before the next assertion of that signal. Similarly, there must be at least 100 pixel clocks between the deassertion of FVAL and the next time that it is asserted. Is this correct?
I am not at all clear on the second requirement. Does this mean that I must toggle LVAL four times before each assertion of FVAL (toggle only when FVAL is false)?
Must DVAL be true when LVAL is toggled?
Must I wait four clocks between each assertion of LVAL, which would be indicated by the first requirement?
Is there a minimum number of clocks that LVAL must be asserted when I do this toggling?
What, exactly, does "Non Continuous Line Enable" mean? I keep LVAL asserted during the entire line time (DVAL is asserted coincident with LVAL). Changing this setting has no effect.
Of course the Camera Link specification itself has no timing diagrams or information whatsoever.
Any help is appreciated.
