Hello,
we're preparing to grab a custom camera with our PCI-1422 frame grabber. I want to pass along the requirments for sync signals to the camera designer so that we'll be able to easily grab the video with a new .icd that we can define.
I would like to know what the miniumum are for both the frame and line invalid periods. This is the time where either sync signal sends a pulse where there is no data being transferred but is signaling the board that data is coming.
Also, I would like to know if the pixel clock needs to be active during the invalid or pulse period.
Based on other cameras, it seems like the sync pulses should be say a minimum of 4 pixel clocks long and the pixel clock should be active
. We're probably OK with this assumption but it would be good to know what the real requirement is so that we can get the data over accurately and reliably.
Thanks for your help,
Wes