Minimizing I/O Latency for communications

[drlava]

Hi all, I'm investigating whether it is possible to use nidaqmx in an experimental bidirectional analog communications situation.  The requirement is that input to output latency should be no more than 10ms when sampling at 50kHz or above.  I have a USB-6343 multifunction DAQ.

I've modified one of the code examples to do a simple basic I/O latency test.  It samples an analog input using an EveryNCallback and loops that to an analog output (using an every N callback) as fast as it can.  The buffer sizes and sample rates can be adjusted to test the limits of the nidaq setup.  The problem is.. even with small buffers set, the code/device can't get the latency below about 40ms.  What may be happening is that it's limited by the hardware FIFO configuration on the USB-6343 device.

I have searched for possible solutions to adjusting the use of the onboard FIFOs and have found some intriguing settings that may or may not help this use case:

Attributes:

DAQmx_Buf_Output_OnbrdBufSize

DAQmx_Buf_Input_OnbrdBufSize (read only)

DAQmx_AI_DataXferCustomThreshold

DAQmx_AI_UsbXferReqSize

DAQmx_AO_DataXferMech

DAQmx_AO_DataXferReqCond

DAQmx_AO_UsbXferReqSize

DAQmx_AO_UsbXferReqCount

And the usual functions:

DAQmxCfgInputBuffer()

DAQmxCfgOutputBuffer()

Here's the issue: there are too many options and too little documentation on them to attempt to fiddle with these blindly to see what combination of settings, if any, will acheive the performance I need.

I have attached the current test code.  Usage: probe the input and output channels (0) with a scope and see how long it takes for a pulse on the input to be presented on the output. 

Could anyone who has experience with this buffering latency question, or an applications engineer grant assistance? thank you!

[Alex-D]

So your system as I understand it is that you want to measure the latency of transferring an input signal to an output line. If this is the case then what could be occurring is that the actual data flow is from the input channel through the USB to the computer back through the USB and to the output. Due to the nature of Windows we can not guarantee the latency of that operation. Only on a real time or an FPGA system can that be guaranteed. It could be possible to have an input trigger an output signal and that would have a lower latency but the transfer of that signal from input to the output should be going through the connected computer and thus would have an unpredictable latency. If I am misunderstanding the way your system is set up please explain it further and I may be able to provide further insight.