10-03-2006 12:13 PM
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10-04-2006 07:15 PM
10-13-2006 04:11 PM
Sorry for the delay, I've been working on other items.
OK so as I understand it you are trying to control a stepper motor (based on that's what the 7330 does) and you have it in closed loop (which is why you have an analog and digital signals) and are reading back the analog and digital position data.
Clarification: I am reading the digital position data from the encoder and analog voltage from a force transducer that will vary over the course of the movement (the force will be all over the place during move)
Both of which are being read back by the 7330 and then the digital signal from the encoder you are passing via RTSI to the DAQ board and that is where you are reading and recording those values.
Further Clarification: Only the digital encoder signal goes back to 7330 and then is routed over the RTSI. The analog signal goes striaght into the DAQ.
Additionally, the digital encoder signal gets routes over RTSI to PFIs 8,10,9 that are counter 0's inputs. I then set up a DAQmx Create Channel (CI Linear Encoder) event to sample the counter in step with the analog input.
I guess it would be pretty hard to see if there is a missing pulse looking at the TTL signal on the 7330's user defined digital lines...but what if you wire the siganl directly up to the DAQ board? any change?
Have not tried, and probably won't (I'll explain why I won't try below)
and in your example the count goes from 12 to 14 and there is the 0 where 13 should be...is this always the case? does it keep the correct count? and is it always at the same number?
The count doesn't skip #s, it just goes 12 12 12 12 0 12 12 12 13 13 13 14 14 14 (I need to check this behavior more, will do that next week)
Count is correct
Not at the same #
-Since there is no # skipping, or I can just interpolate what 0 should be, I'm hesitant to rewire things.
Also, does the analog signal have anything to do with the digital signal you are sending to the counter (other than that you want them to have the same sample clock)
The signals have nothing to do with each other at this point because I am just debugging the system with a fake input
10-16-2006 02:28 PM
10-25-2006 10:31 AM
10-26-2006 01:20 PM
10-27-2006 08:50 AM
10-31-2006 04:07 PM