Hey annapurna,
From what I understand you are doing a HW Timed 1 Sample Analog Output generation, have configured a Start Trigger on PFI1, and have configured an External Sample Clock on PFI1. You should be able to get rid of the pretrigger requirement by not setting the Start Trigger. Setting the Start Trigger to PFI1 means that the device will wait for a rising edge on PFI1 before it begins the generation.
Also, you will have one rising edge for each voltage each in the list. If you are receiving a timeout error this means that the device is expecting a trigger and is never receiving it. I am assuming you are doing this in a loop so you may be iterating one too many times in the loop. Do you mind posting a screenshot of your block diagram?
Regards,
Chris Delvizis
National Instruments