05-29-2008 04:05 PM
Hi Vectrix,
So it sounds like you need to output a repeating sequence of values timed to an external 21 kHz clock. To do this I would recommend taking advantage of analog output regeneration. This will let you write the output sequence to the buffer once and then the card will output the sequence over and over. You can time this to be synced with an external clock. An example of this can be found in the NI Example Finder. In LabVIEW go to Help >> Find Examples… >> Hardware Input and Output >> DAQmx >> Analog Generation >> Voltage >> Cont Gen VoltageWfm – Ext Clk.vi. The external clock will be your 21kHz signal and you can replace the examples waveform with your repeating sequence.
One thing I noticed in your VI is that you have 300 wired to the rate terminal in the timing vi. When you are providing an external clock the rate terminal should be set to the highest frequency you expect that external clock to run at, in your case 21000. Also you will want to set the sample mode to “Continuous Samples”. Please let me know if you have any questions and take care.
Thanks,
05-29-2008 04:28 PM
05-30-2008 03:32 PM
Hey Vectrix,
The way the example I showed you and hardware timed analog output works is that on each edge of the external clock 1 sample from the buffer is output. It does not output the entire buffer on each edge. When the end of the buffer is reached it starts over from the beginning. So if you write 0,3,6,9 to the buffer on the first clock edge 0 will be output. On the second edge 3. Next edge 6. Then 9. On the fifth edge 0 will be output again and so on. This sounds like the behavior you were looking for. When using an external sample clock the output will be timed to that clock and only output a sample on the active edge of that clock. You still however need to set the rate terminal of the timing VI with the highest frequency that you expect that external clock to run at. This is so the drivers know how large of a buffer to allocate for the task. This value is used to setup the timing of the acquisition only when using the internal sample clock. If you provide an external sample clock the output timing will depend solely on that clock. I hope this helps and let me know if you have any questions.
Thanks,
06-06-2008 07:04 PM
07-02-2008 05:43 AM
07-03-2008 04:38 PM - edited 07-03-2008 04:39 PM
07-03-2008 05:09 PM
07-18-2008 10:56 AM
Hi Jeroen,
I have attached a vi that does exactly what you have described in the other forum. I have not seen any delays in the response while running the code on my system.
The vi is a modified version of the example library.
Hope this helps,
Vectrix