Analog Output Optimized Driver/Buffer/Inverter/Non-Inverting Amp Op

[Foreshadow20]

What would be the best implementation for NI DAQ buffer/driver for a generated sine wave?

I see a lot of circuit implementations for AIs, but none for AOs.

I will use my setup as an example:

FPGA 7853R has an impedance of 0.5ohm for analog outputs.

The generated signal is a sine wave (~3KHz) and it can be inverted.

The connected circuit is susceptible to low voltage variation (1 mV) (let's assume the FPGA AO's tolerance to be ±0 for this thread).

From the information that I gathered:

A feedback resistor should be the same as the source impedance (Inverter and non-inverting)

Inverting divers are better for low impedance input and non-inverting for high impedance input

From my analysis, it seems that the an inverter with a 0.5ohm resistor would be the best implementation (#1).

I MS Painted a few possible implementations that came up while researching:

[Henrik_Volkers]

Your No 1 and 2 wouldn't work 😄

For an inverting bufer you would need (+) tied to GND and two equal resistors ,a feedback resistor (out) to (-) and (-) to AO . The value is defined by the max current the AO can supply (the 0.5Ohm is the dynamic output  impedance!) , 10V and 1mA give 10kOhm.

The non inverting buffers would work.. however you need gain 1 stable OPamps ... (the datasheet is your friend) bandwidth according to your needs and some more buffer caps and maybe output network if you drive a capacitive load (cable).

[Foreshadow20]

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@Henrik_Volkers wrote:

Your No 1 and 2 wouldn't work 😄 

HAHAHA

I tried to get the post done before the end of the day and just swapped the +/- to save time and didn't bother to look down at my hand drawn schematic.

The OP Amp used is the ths4062 and should be stable. We currently have the amp op implemented as non-inverter for the high side (no resistors), but someone screwed up the low side of the signal and swapped the FPGA's AI with the AO (where the AO is straight through instead of passing through the buffer and the AI is useless at the Amp Op (+)). So while we are at it to fix the low side, I suggested that we might as well implement an optimized circuit for the FPGA's AO.

The Amp Op circuit can't have any type of gain other than a perfect 1. Having 2 resistors at 1% tolerance stack up to 1.41% (RSS) can give an error of 0.5mV RMS at the higher range, which the circuit has a low and high side so the error stacks up even more.

I was thinking that adding only 1 resistor in the feedback could optimize/compensate with the FPGA's output impedance.

[Henrik_Volkers]

Noninverting amp : Rf should be 270 Ohm RTFD (read the fantastic datasheet)

(But a input bias current of 1µA will lead to ~1.3mV offset)

Inverting amp with gain 1 will need two matched resistors 🙂  fortunately you can buy a matched pair .. I think linear.com have them ...

http://www.analog.com/en/products/analog-functions/precision-resistor-network/lt5400.html

http://www.ti.com/lit/an/sboa092b/sboa092b.pdf

[Foreshadow20]

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@Henrik_Volkers

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Noninverting amp : Rf should be 270 Ohm RTFD (read the fantastic datasheet) 

The 270 ohm Feedback resistor made me look further into the feedback resistors (which some sources indicate that it should be the same impedance as the source). Someone mentioned a few days ago that 270 ohm resistor seem to mainly be used for the higher range of frequencies where the ringing may occur, which could improve the FPGA signal from its "bit steps".

Thanks for the TI handbook, it is quite informative.

So the best implementation for DAQ/FPGA Analog Outputs Sine Wave generation would be an Amp Op Inverter where the resistor pair would be the Max Voltage Range / Max Current Drive?

FPGA 7853R: ±10V/2.5mA = 4K

PXI-6723: ±10V/5mA = 2K

[Henrik_Volkers · Accepted solution]

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@Foreshadow20So the best implementation for DAQ/FPGA Analog Outputs Sine Wave generation would be an Amp Op Inverter where the resistor pair would be the Max Voltage Range / Max Current Drive?

FPGA 7853R: ±10V/2.5mA = 4K

PXI-6723: ±10V/5mA = 2K

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No, it's not wise to work close to the current drive limit.. I would choose 10k for all ...

If you build a differential input 1:1 buffer (figure 26 in the handbook) you can choose the inverting/noninverting function by swapping the input lines. Or use two buffers for a symetric buffered output.With 10k resistor networks you end up with a 5k load , still fine for both drivers.

[Foreshadow20]

We changed to an inversing 1:1 gain with 10K 0.1% resistors.