Beginner: Convert number to binary

[ThSa]

Andrea,

thanks for the explanation. But there are still some open points which needs to be resolved before.

Is the SineWave block a reference signal for a specific algorithm or do you wanna replace the the signal from the SineWave block with the signal from your LabVIEW code?
What is the inport "Vlvdt" good for (is this the input for the signals from LabVIEW)?

You've mentioned that you want to extract the entire signal generation from Simulink. In this case it gets a bit complicated to cover all points in LabVIEW. Depending on your LabVIEW knowledge it might get hard to implement.
An alternative would be to work with a multiport switch and with several specific signal source blocks in Matlab. In this case you don't need to think of LabVIEW, LabVIEW Real-Time components and programming techniques, etc.
Please let me know what you think about.


Thanks,
ThSa

[Odryx]

I Think that you understand what I want do!

I'd like replace the "Sine Wave block" with the signal reference generated in LABView.

The Port Vlvdt represents the Input for the position transducer.

The final configuratio will be:

Reference signal, that replace the sine wave block, by LabVIew

Vlvdt, position transducer.

I'd leave the solution with multiport switch only if I didn't succeed with LABVIEW

Thanks

[ThSa]

Well, in this case I have one last question :-)
Is the signal generation supposed to be deterministic (the signal generation is processed on the RT desktop PC in the driver.vi) or non-deterministic (in this case the signal generation is processed on the Windows PC and the values are send via the SIT server to the driver.vi)?

As you already know, in case of a deterministic signal generation the sinewave block needs to be replaced by an inport.
If you wanna cover both the deterministic and non-deterministic stuff, connect an inport and a constant block (value = 0!) to a sum-block. This way provides the option to run either this or that scenario.

I will implement an example by tomorrow.

Thanks,
ThSa

[Odryx]

Ops I forget to remark that I need to generate a determinist signal as  you say exactly the signal generation is processed on the RT desktop PC in the driver.vi!

Thanks for your disponibility. You're very helpful!!

Thank for all

[ThSa]

Andrea,
here we go...
Attached please find a sample project which won't be executable in the current state it is (saved back from 8.5 to 8.2), but this isn't important.
The project simply shows how to cover your requirements.

At first you need to replace the SineWave block in the simulink model by an inport.
The inport number shown in the Simulink environment is related to the 1D array of the base-rate-loop.vi.
The index of the inport in the 1D array is the number shown in Simulink - 1.

For example: Inport number in Simulink is 1. The relating index number in LabVIEW is 0.

In the sequence "Read Code" in the _base rate loop.vi I've added a specific user code which provides the signal generation. The way it works is a bit different than your approach, because I've used point by point operations. Using those functions you may use the entire signal generation framework directly in the base-rate-loop.
If this is not the one you are looking for, the 2nd option would be to have 2 VIs. One VI for the waveform generation and another VI which is reading index by index the waveform array. The communication between those two VIs needs to be established by using RT FIFO.

The communication between Host and Driver, respectively base rate loop.vi, is implemented in a very easy manner -> Shared Variable with the attributes network-published and RT FIFO enabled. You may replace the SVs by TCP IP or whatever you are thinking of.

If you have any further questions, please come by.

Thanks,
ThSa

[Odryx]

Hello Thsa,
Sorry If I don't reply before but I'm working on my graduation thesis.
I understand the logical plan of attached VI and I'm tryng to retrace every step.
I have few question:
1) I deside to Deploy the MODEL ON THE target. iF I add the VI creates by SIT in a project and I run the VI, LV detect an error.
I'm trying to Solve this by using  "BUild Specification". Is it the right way?

2) How Can I check that The Sistems works really in real-time conditions?

Thank for the helpfulness

Odryx

[ThSa]

I guess that the error is related to the missing model DLL?
Running the driver VI manually requires to deploy the simulation model manually via FTP to the RT target (folder: C:\ni-rt\system)
Afterwards run the driver VI and then the Host VI.
If the error is caused by multiple connected projects to the same target, ensure that no project explorer does have an active connection to the target.

What do you mean with "check whether it runs really in RT conditions". Do you wanna measure the jitter between the loop iterations?
If yes, the best and most thorough way would be to use the execution trace toolkit. A simply alternative would be to add a clock to the base-rate while loop to measure the iteration time. Another option would be to monitor the HW output by using an oscilloscope...

ThSa

[Odryx]

Wow but your are a flash!!!!!

Another Question, In The Base Rate Loop.vi the third row of the unbundle Block is named: "Background Loopsync"

Excuse but I don't understand what does it means and where can I fin it!

Thanks

[Odryx]

Following the procedure releated by you the VI work properly.

The only doubt is that the VI is executed on the RT but the interface VI suggest that it'is run on My computer? (The little box down left)

[ThSa]

It seems that the problem is related to the fact, that you are working with my example which is done in LabVIEW 8.5 and SIT 4.0.
I've mentioned, that I saved it back to 8.2. Concerning this fact not all SubVIs will match from your SIT version.
Actually, the only VI you need is the one for the signal generation, all others are used to present to you the entire framework.

Regarding the execution target, I think you have opened the top level VI from "My Computer" therefore the execution target is wrong.