CPU load increasing with LabVIEW 8.6 Realtime Application

[kmc]

I recently upgraded from LabVIEW 8.5 to LabVIEW 8.6.  When I rebuilt my realtime application in LabVIEW 8.6 and ran it on my 8106 Embedded Controller, I noticed that the CPU load slowly increases.  If I run my VI (the one I used to create my realtime application) from the front panel on the RT controller, I do not see a CPU load increase.  Note also that in LabVIEW 8.5 I was able to run from the front panel and as a realtime application without any issues.  Also note that nothing has changed other than upgrading to LabVIEW 8.6.  I have attached sreen shots of the CPU load, both were taken after running for about 30 minutes.

Thanks, 
Kevin C. 

[Kameralina]

Hello Kevin,

That sounds like quite a strange situation.  Is your code large?   Does it require hardware or is it something that we could run at our end?

 If you can, please post the 8.5 and 8.6 versions of your executable and code so that others can run the code as well.

Have a great day!

[kmc]

Hi FieldKam,

Yes the code is large and it does require hardware.  I think I have narrowed it down to a loop that is calling to read from an FPGA DMA FIFO via an Invoke Node.  I am attempting to recreate the problem in a simpler application however, I am now running into another issue.  When I build my application and choose Run as Startup, I now get an error -823 "Loading tlsched_library.  Cannot load scheduler library on the targert" after the RT box reboots.  I also get the error if I just attempt to run the VI from the front panel on the RT box.  The error occurs when attempting to use a timed loop.  Again note that I didn't change my VI, simply built as an RT application and then tried to deploy.  Any ideas on why I would be getting this error???

Thanks,

Kevin C.

[kmc]

The issue seems to be with the call to the FPGA DMA FIFO read via the invoke node.  My RT VI is continuously calling to read the DMA FIFO looking for status.  The FPGA VI is not writing anything to the FIFO therefore the host VI will timeout, ignore the timeout error, and call to read the FIFO again.  If the RT VI is run/deployed from the front panel, there is no issue, that is there in no increase in the CPU load.  If I build the RT VI as a RealTime Application, set it as startup, and deploy it, the CPU load will slowly increase.  Attached is a copy of a simple RT VI which exhibits this behaviour.  I have also included the FPGA VI which doesn't do anything but give access to the FIFO resource.    

Thanks,

Kevin C.