I've never used LV FGPA (it's on my todo list), but if I wanted to route multiple signals to a bunch of different outputs in an FPGA, here's a simple way to do it:
Let's say you had 32 output ports (X(31 downto 0)) and one channel A that you wanted to programatically route to one (or more) of the pins. First, you could declare a 32 bit "mask" register in your design, and make it accessible to the top level or whatever you're using to change your route.
Then, AND each bit in this mask with your channel A:
X(i) = A AND MASK(i); --where i is 0 to 31
In software this would be a FOR loop, but since youre in an FPGA this can be done all at the same time (and if you use a FOR loop for this, the fpga gods will kill a kitten).
Now, when you write the value 0x000000001 to your mask register, the least significant bit of X will follow the signal in A and the rest will stay at 0:
X(0) = A AND 1 = A
X(31 downto 1) = A AND 0 = 0
Note that if you wrote 0x00001001 you would get two lines to follow signal A.
What if you also had signals B, C and D? Just declare four masks and OR them all together at the end!
Amasked(i) = A AND A_MASK(i);
Bmasked(i) = B AND B_MASK(i);
Cmasked(i) = C AND C_MASK(i);
Dmasked(i) = D AND D_MASK(i);
X = Amasked OR Bmasked OR Cmasked OR Dmasked;
So if you were to write 0x00000001 to A_MASK, and 0x10000000 to B_MASK, you would end up with your lowest line following A and one of your higher lines following B. Note that if you wrote overlapping masks to the registers you would end up with the OR of your signals (if A_MASK and B_MASK both got 0x00000001, the lowest line would output "A OR B"). You could add some logic that checks for mask collisions and reports back with a boolean if you'd like.
Using that method you can pretty cheaply route around a few signals and change them on the fly.
Hugs,
memoryleak
PS I think there's a structure in LV FPGA that allows you to tell it to not place registers between logic... I think that for a small number of signals this app is a great use for that feature. You can or-mask 8 signals together in two levels of LUT4s (Virtex4 and older) and 18 in two levels of LUT6s (Virtex 5). Two levels of logic should be super duper quick and not cause timing issues at 40mhz. (You're probably safe with more, there is no hard and fast rule)
