Control loop from task is not supported by PCI6229?

[eFang]

I have NI6229 PCI card and 2 SCB-68 boxes. Labview 8.5 pro

Manually I test the mininum cycle with "Generate Signals - Counter Output" and found that 100ns is good enough for me. Actually I only need 100ms.

I wanna use the clock on PCI 6229 to control a DO port to generate a pulse(0V/5V) to my instrument.

Here is my VI and screen snapshot.

When testing, an error keeps poping out:

control loop from task

Error Code: -200452

Error -200452 occurred at DAQmx Create Timing Source (Control Loop From Task).vi:1
Possible reason(s):
Measurements: Specified property is not supported by the device or is not applicable to the task.
Property: ControlLoopFromTask.SleepTime
Task Name: _unnamedTask<17>
 

I modified vi several times but it didn't work. What's wrong? Is the "control loop from task" not supported by PCI6229?

Besides, I think I should use only one digital boolen output in the loop. But I don't know how to wire if I use one.

Thanks for your time!!!

[Chris_K_]

Hello eFang,

Thank you for posting on our discussion forums.

First of all, I notice that you are using the counter output task to generate the clock that you want to use to drive the time loop.  This is not supported and it is the reason you are getting the error you describe. In order to accomplish what you want a manner similar to the VI you have sent me, you must use an analog input task and wire that to the DAQmx create timing source (This is outlined in the detailed help for the DAQmx create timing source VI). This gives you access to the cards sample clock, and it can be used with the timed loop.  I have modified the VI that you attached to create a VI that uses the sample clock to time the timed loop, and it generates a continuous digital pulse train.

I am not sure exactly what you are trying to accomplish for your application .  If you just need a continuous or finite pulse train, I would suggest using the Gen Dig Pulse Train-Continuous.vi or Gen Dig Pulse Train-Finite.vi respectively from the example finder.  This gives you more control over the type of pulse that you produce for your instrument.  It allows you to control duty cycle, and other properties that cannot be selected with a simple digital line.

If you require further assistance can you let me know a little more about your application.  For instance, exactly what are you trying to output to your instrument?  Any information will be helpful in finding a solution.

Have a great day

Chris_K_

[eFang]

Thanks for your instant reply.

I still have several questions:

1. Does every AI have its own clock separately?

2. What's difference between counters and timing sources?

3. What's the meaning of sleep time here? We don't need it, right?

4. About my application:

When it's running, it's allowed to set up the freq, the timing source, number of the pulses and idle state.

Frequency: 10ms-1s is usually used for us.
Timing source: generally we use clock on PCI6229 to get more accurate pulse
Number of pluse: about 1-100
Idle state: usually we use "low" for this.

When setup is done, I click "Start" to output the designed pulse. I may either wait for it to execute defined times and then stop

automatically, or I may click "Abort" button to exit. And I may change some parameters to run the program again. Obviously, we need

finite pulse train.

The signal I'm trying to output to our instrument is 0V and 5V alternately. For example, output 0V for 5ms and then 5V for 5ms and

then again 0V for 5ms and so on.

I used a scope to test the output using the clock from Ctr0 and Ctr1 and found out that the accuracy of 100ns is acceptable for us,

even if we usually use some milliseconds as the freq.

Besides, I read your vi and the Gen Dig Pulse Train-Continuous.vi and Gen Dig Pulse Train-Finite.vi carefully. Your vi is more close

to what we want. But we need to control the freq, counters, idle state, duty clcle, number of pulses, etc, just like the front panel in Gen Dig Pulse Train-Finite.vi.

So could you help me to merge them into one vi? Thank you in advance for your help!!!

[Chris_K_]

Hi eFang

No all since all the analog input channels share the same multiplexer, all ai channels use the same timing clock.  However the digital I/O and the analog output each have their own timing clock.

A timing source sends ticks to a timed loop. The timing source is based on signals a device generates. Those ticks determine when the Timed Loop executes.  Check the detailed help for the DAQmx Create timing source vi.

Counters are hardware controlled registers that are designed specifically to increment or decrement a count register.

Typical counter applications involve anything that can be counted or can make use of the load registers to generate on the output pin. Again additional information can be found in the help for the DAQmx Create timing source vi.

·         This includes Pulse, Semi-Period and Period Width Measurement of Input Signal

·         Frequency Measurement

·         Pulse and Pulse Train Generation

·         Position & Velocity Measurement

Sleep time is the number of microseconds that the Timed Loop sleeps after each sample clock pulse. Depending on your specific application, it may or may not be needed.

In general it is not recommended to use the abort button, as this leaves references hanging.  Using the stop button, stops the current timed loop, but is allows the rest of the VI to finish and end in a desired manner.

As for your application, you can control all the parameters that you mention with the Gen Dig Pulse Train-Finite.vi so I am unsure what you are trying to merge together.  Can you please elaborate?

Thanks

Chris_K_

[eFang]

Hi, thank you very much for your detailed explanation.

In Gen Dig Pulse Train-Finite.vi, the pulse is outputed to Ctr0 directly which I don't want. I think the counter(ctr0 or ctr1) should be used to control another digital output, which in turn will control the instrument. It is a digital output, not ctr0 itself, that controls the instrument.

I want use Counter 0 or 1 to control one digital output. And this digital output will generate pulse to control the instrument. The pulse should come from the clock on pci6229 card and be much precise.

You can see what I want in the attached vi file.

Thanks in advance for your help.

Yigang Fang

[Chris_K_]

You can use the Gen Dig Pulse Train-Finite.vi to create a finite pulse train using the counters on your card (a finite pulse train uses 2 of the DAQ cards counters), to clock your digital output.  Look at the attached VI, it uses a finite pulse train to clock the digital output task.  Note that this VI internally routes the ctr0 line to the clocking source of your digital output task.

Chris_K

Message Edited by Chris_K_ on 01-20-2008 10:37 PM

[eFang]

Thank you so much for your help. Following your instructions, I've solved the said problem already. It runs perfectly.

By the way, how can I put indicators to show the DO voltage, AO voltage and number of cycles simultaneously while running these tasks? Is that possible to display them in one chart?

Thanks in advance.

[eFang]

Attached is my vi.

[Chris_K_]

I am happy I was able to help you. 

There is no simple way to display what is being outputted on the AO, DO and Counter tasks.  You can just display the values that you are inputting to your AO write VI, but that will not give you any relational information. 

One way you could do this is to create an AI task that has three inputs, and then wire the counter line, the DO line and the AO line to three AI lines and perform a continuous analog acquisition.  Then you will be able to see all the outputs in relation to each other. 

Cont Acq&Graph Voltage-Int Clk.vi, from the example finder should be a good starting point.

Have a good one

Chris_K    

[eFang]

I know what you mean. As you can see in the attached file, I create a new "row" starting with "AI Voltage", and then "Sample Clock" and "Analog 1D wfm NChan NSamp". But it's confusing me how to create an AI task that has THREE inputs. I tried to wire them to the physical channel but obviously it's wrong. I read that example you mentioned very carefully but it's sort of different. Could you do me a favor to make this a little clearer?

Thanks for your time and patience.

Yigang