DAQ timing specifications explained (PXI 6281)

[alysko]

Dear NI Tech Support,

On the example of PXI 6281 specifications I tried to characterise the A-D converter (see below). Could you please correct where I am wrong and add what is missing in the effects and their explanations.

A. Timing accuracy ......................... 50 ppm of sample rate

a)      Setting the sampling rate to 10 kS/s will result in 10kS/s*50ppm= 0.5 Hz uncertainty in the true frequency of a sinusoid generated or acquired.

For applications relying on FFT, this means that there is no point trying to improve the frequency resolution by observing for longer than 1/0.05=20s.

b)      Important for phase-sensitive applications utilising non-synchronised oscillators: phase drift of 50 ppm may eventually change the phase of a signal by as much as 180 degrees (loss of coherence). Sampling at the rate of 10 kS/s will result in 1 seconds of coherence time.

c)   Jitter of 1/(10kS/s)*50e-6=5ns  - see http://en.wikipedia.org/wiki/Analog-to-digital_converter - not good for digitizing 44.1 kHz or even 1 kHz at 18bits with PXI 6281. Here I am unsure about the applicability of the term JITTER. Please comment.

B. Timing resolution ....................... 50 ns

In phase-sensitive applications, this will create a small error in measured amplitude due to the phase difference. Assuming signal frequency of 1 kHz, for co-phase channel (I), the error is limited to 1-cos(2*p*1000*50e-9)=5e-8 (equiv 24 bits), whilst for quadrature channel (Q), the error is limited to sin(2*p*1000*50e-9)=0.0003. The latter corresponds to resolution of 11.7 bits. Both are the worst case scenarious and the actual error is due to the distribution between these values?
Jitter of 1/(10kS/s)*50e-6=5ns  - see http://en.wikipedia.org/wiki/Analog-to-digital_converter - not good for digitizing 44.1 kHz or even 1 kHz at 18bits with PXI 6281 (e.g. 1.2ns jitter required for digitizing 1kHz signal with 18 bits). Here I am unsure about the applicability of the term JITTER. Please comment.

C. How are these parameters (see above) related to the reference oscillator (which also has an external input, giving the opportunity to improve the frequency stability)?

Thanking you in advance.

Sincerely
Albert

[Speedy_Badger]

Hello Albert,

Is there a specific application you are attempting to develop with the PXI 6281? The specifications you have listed are for the most part as you have interpreted them to be. Let me respond to each one as best as I can.

A. Timing Accuracy.

Your calculations for the 10kS/s case were correct and the accuracy will be +/- 0.5 Hz. This is a worst case specification, so in actuality the error could be much smaller. It is certainly possible that over a long period of time (i.e. 5 days) that you could possibly see a phase shift as extreme as you have described.

B. Timing Resolution.

The 50 ns resolution is based on the 20 MHz timebase of the onboard voltage controlled oscillator (VCXO). There are two recommend options if you would like better resolution and accuracy. I believe these options also answer your third question about external timebase references improving stability and resolution.

 1. Use a counter to generate your sample clock. This gives you access to an 80 MHz timebase. The resulting resolution is then 12.5 ns.

 2. Use an external timebase. Since you are using PXI as your platform, you have access to the backplane clock within this chassis. You are then capable of implementing a timing engine such as the PXI 6608 Counter/Timer board or the PXI 6652 Timing and Synchronization board. The advantages of each are listed below:

  The PXI-6608 has an improved timebase stability of 0.075 ppm and a 1.25 ns resolution.

  The PXI-6652 has a 105 MHz timebase allowing for 10 ns resolution. This also gives you access to TXCO and OCXO which gives you a long term stability of 1 ppm or 50 ppb/year respectively.

A final option would be to use Dynamic Signal Analyzers for your application. These boards have an accuracy of 25 ppm. You can find information on our DSA boards at here.

Regards,

[Adam_U]

Albert,

It sounds like you might be interested in synchronizing multiple channels or systems. If that's the concern, the timing resolution of 50ns won't play much of a part. I believe the 50ns resolution is most impactful to rounding error when trying to divide down the 20MHz timebase. If rounding must occur, it would be the same between multiple systems. You could calculate if your target sample rate is an integral divisor of the base clock frequency.

As to the base clock frequency, you could override the PXI chassis CLK10 (10MHz clock) which is matched trace length to every slot. As Chris mentioned, you could use this to get better accuracy (if you can't share CLK10 directly) to get a closer frequency reference on separate systems.

-Adam

[alysko]

  Thank you for your answers. My application is in accurate digitization of an analogue signal and digital signal processing.

-1) How does the frequency selection work? Say, there is 20MHz oscillator. Then you need to divide the frequency.

0) How do you do it?

1) Can I interprete the resolution as an effective precision (repeatability)?

2) I did not follow the advice on counters. Are you talking about additional modules?

3) Could you please comment on the jitter?

Thanks!

[alysko]

I wanted to add my interpretations and ask for more of you comments on it:

5) Should I perhaps look at the timing resolution as a measure of the ability to shift 2 signals with respect to one another?

5.1) Generating signals: min step in time or min time difference between 2 or more signals?

5.2) Acquiring signals: best accuracy of determining the time delay between 2 signals?

Thanks!

Albert

[Speedy_Badger]

Hello Albert,

-1) How does the frequency selection work? Say, there is 20MHz oscillator. Then you need to divide the frequency.
0) How do you do it?

Basically the 20 MHz timebase will be divided down by integer values. The DAQmx driver takes care of this operation for you depending on how you set the parameters of your application. Since this is integer division you will not be able to achieve highly accurate timing in relation to frequencies such as 44.1 KHz.

As a side note, the DSA boards that I mentioned in my first post would be capable of accurately acquiring specific frequencies such as 44.1 KHz. 

1) Can I interprete the resolution as an effective precision (repeatability)?

The 50 ns timing resolution specification is derived directly from the 20 MHz timebase.
 
2) I did not follow the advice on counters. Are you talking about additional modules?

Yes, basically what I was referring to was using additional modules such as the PXI 6608 and PXI 6652. These modules provide a more accurate timebase using TCXO and OCXO which you could then export to the M-series device. This would improve the overall resolution that you have access to. My comment on the counter was to show that the 50 ns specification that you brought up is directly related to the fact that your analog input sample clock is derived from a 20 MHz timebase.
 
3) Could you please comment on the jitter?

The application of the term jitter can be related to the fact that clocks will be imperfect. We can then characterize this imperfection as jitter. The more accurate the timebase is, i.e. from a timing and synch module such as the 6608, the lower the jitter.
5) Should I perhaps look at the timing resolution as a measure of the ability to shift 2 signals with respect to one another? No. timing resolution is directly related to the inverse of your timebase frequency.

5.1) Generating signals: min step in time or min time difference between 2 or more signals?

5.2) Acquiring signals: best accuracy of determining the time delay between 2 signals?

I am not entirely sure what you are trying to ask with these last two questions. While you mention DSP and signal acquisition, I feel a little more detail on what you are doing will allow me to translate these specifications more clearly. Are you worried about synchronicity between signals or devices like Adam suggested? Are you simply concerned about being able to accurately acquire specific signals and bandwidths?

Feel free to post as much detail as you need to express what you are thinking.

Regards,

[ChrisR.]

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Could you please comment on the jitter?

The application of the term jitter can be related to the fact that clocks will be imperfect. We can then characterize this imperfection as jitter. The more accurate the timebase is, i.e. from a timing and synch module such as the 6608, the lower the jitter.

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For more info on jitter, see my response to your duplicate post here: http://forums.ni.com/ni/board/message?board.id=250&thread.id=35188

I've never seen any significant jitter artifacts with the M series boards. Of course there must be some if you look hard enough.

I also need to clarify that clock accuracy and jitter are not related at all. While good accuracy and low jitter often go hand-in-hand, there is no guarantee that good or bad specs in one parameter will translate to the other parameter. And even if you managed to get a perfect timebase to clock the 6281, the timing could still be corrupted by other signals on the board.

Which leads me to echo what Chris B. said: if you could tell us exactly what you're trying to do, we could let you know if the PXI-6281 is a good product to do it.

Chris R.