Finite analog reads within a hardware timed loop

[brian_g]

Hi all,

I'm a bit stumped as to the best way to configure Labview to do the following task:  From a hardware timed loop (using a digital edge detector), do a voltage measurement (PCI-6220) on a couple of channels. We need the DAQ buffer to be empty and not contain values from before the trigger so we're using finite sampling mode.   The data is then passed off to a queue for processing elsewhere in the program.  Initially I had the timed loop trigger signal also triggering the finite read but what would happen would be:  timed loop gets triggered, the DAQ gets it's "start" command, it reads on the next trigger signal, etc.  Effectively we were getting DAQ reads every other trigger signal.  

I then tried something a little smarter, we made the trigger signal longer (1 ms), and had the finite read triggered on the falling edge of the pulse.  The idea was the rising edge would trigger the execution of the loop, the finite read would be called, and the falling edge of the trigger would then trigger the read.  This doesn't work either, we still can only get the system to do reads every other trigger signal.

I have some questions...is there a proper way to reliably do finite acquisitions from inside a hardware timed loop?  Do we need different DAQ hardware (this would be o.k., we need it to work more than we need to use the PCI-6220!)?  If I were to set the DAQ to run in continuous mode, can I clear its buffer before starting the read? Thank you!

[Chris_W.]

Hello,

I am a bit unclear on exactly what you are trying to do. What do you mean when you are saying your are using a hardware timed loop, using digital edge detector? Are you using a Timed while loop in LabVIEW? Is this on an RT system? 

From what it sounds like to me, and correct me if I'm wrong, but it sounds like you have some timing signal, i.e. pulse train, that you are somehow using to time your timed while loop and also using to trigger your finite acquisition. These two things seem to me that they should be separate. 

What is the speed at which you are acquiring your analog input channels on your 6220? As far as your triggering conditions are concerned, it sounds like you just need a start trigger with a finite acquisition in DAQmx. There are examples in the NI Example Finder that do this under the folder path Hardware Input and Output>>DAQmx>>Analog Measurements>>Voltage>>Acq&Graph Voltage-Int Clk-Dig Start.vi. This VI does a finite acquisition using a digital edge as a start trigger. 

If you are needing to have re-triggerable analog input, then you may be able to use one of the shipping examples in the NI Example Finder that is for re-triggerable AI. Yoiu can find these at the folder path Hardware Input and Output>>DAQmx>>Synchronization>>Multi-Function>>Multi-Function-Ctr Pulse Train Generation for AI Sample Clock.vi. There is a small amount of time that it takes for the counter trigger to re-arm itself between triggers. 

Chris W