Gate generation based on encoder readings

[zhenmeister]

I am trying to use a pci-6602 board to generate a gated pulse using encoder readings as a clock for the gate. 

The period of the encoder pulse around 150usec plus/minus 2%.  Every 2000 encoder pulses I want to start a pulse train with the following properties: low time = 1650usec, high time = 2usec, # of pulses = 3.  I set up one counter (ctr0)  to serve as a gate driven by encoder pulses.  Then I used a second counter (ctr1) to form a retriggerable pulse triggered by a rising edge of ctr0 and paused on low level of the ctr0.  Ctr1 is driven by the internal clock at 20 Mhz.  Because of imprecise timing nature of my gate  I don't seem to be able to guarantee ctr1 starting with 1650 usec low.  IE if the previous pulse was paused in the middle of low state, then the next triggered pulse starts with in the middle of low state.  To remedy the situation I thought of pausing the trigger on [ctr0out NOR ctr1out].  Is there a better solution?  Seems like there should be an easier way to guarantee that my pulse train starts with a full low every time.  I must also mention that I only have one counter left unused on the board.

Thank you,

Yevgeniy

[Kevin_Price]

1. What you're doing with Ctr 1 is called a "finite retriggerable pulse train."  Under DAQmx, when you configure a counter to generate a finite pulse train, a 2nd counter is automatically & silently configured to help with the task.  The counters on your board are paired in the following 4 groups: (0,1), (2,3), (4,5), (6,7).  So if Ctr 1 creates the 3 short pulses, Ctr 0 will also be used by the DAQmx driver.  It won't be available for you to use in any other way.

2. Assuming you go ahead and use Ctr 1 to generate the 3 pulses, you'll need to use your last unused counter (something other than Ctr 0) to generate the trigger signal once every 2000 encoder cycles.  I would just configure it for pulse generation with settings of 1000 low ticks and 1000 high ticks.  Essentially, you'll get a divide-by-2000 clock which will produce a single trigger edge every 2000 encoder cycles.

-Kevin P.

[zhenmeister]

Thank you for the reply Kevin!

1. I was just naming the counters so I could refer to them easier in my post, but you brought up an interesting point which I didn't consider.

2. I think I chose the wrong path by using a continuous retriggerable pulse train with a pause trigger.  Your suggestion is so much simpler! 

Thanks,

Yevgeniy