Issues using Simulated Modules 9231 and 9204 in One Task (with cDAQ-9177) - Channel Order and Sampling Rate Limits

[daniela21]

Hi,

I'm working with a simulated cDAQ-9177 with two simulated AI modules: the 9231 for IEPE (max rate 51.2 kS/s per channel) and the 9204 for Voltage (max rate 250 kS/s total). I am reading from both modules in the same task using continuous samples (batches of 100). I have encountered two problems:

1. Channel order affects the (simulated) readings: If I add the IEPE channels before the voltage channels, the IEPE channels read basically zero and the voltage channels read full-scale noise, instead of the expected sine waves. If the order is reversed (voltage channels first, then IEPE channels), every channel reads the expected sine wave.
2. Sampling rate limitation with ≥5 voltage channels: Starting from 5 voltage channels (regardless of the number of IEPE channels), an error appears saying the maximum sampling rate is 34.13 kS/s. For 5 voltage channels, I would expect the sampling rate to go up to 50 kS/s because this would still be within the 9204’s maximum total rate, and it does not exceed the 9231’s maximum rate either. Also, the maximum sampling-rate value shown in the error does not change for any higher number of voltage channels.

I thought these problems might be related to clock synchronization because the modules belong to different C-Series groups (the 9231 is a Delta-Sigma device while the 9204 is a SAR-Scanned device), but after reading the article "NI: Signal-Based Synchronization of Analog Input C Series Modules with NI-DAQmx in LabVIEW" I didn’t find any explanation for these issues.

Are these conflicts happening only because I'm working with simulated devices?

Notes: With a cDAQ-9179, the first conflict is reversed (the order that works is IEPE channels first, then Voltage), and the second conflict is the same. I am using the most recent LabVIEW version and corresponding drivers (including DAQmx).

[santo_13]

Simulated devices are ideal devices and they are "simulated" and not replacement for real in terms of behavior, it doesn't enforce all the limitations of real hardware.

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@daniela21 wrote: 

Are these conflicts happening only because I'm working with simulated devices?

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Maybe, only real hardware can validate the code you wrote.

[mcduff]

You need to post your code in order for help.

The max aggregate rate of the 9204 is 250kSa/s. So yes 5 channels at 50kSa/s each is possible, BUT, you are using channel expansion and combining an input from your DSA module. Your DSA module CANNOT sample at arbitrary rates, the rates are fixed with respect to the internal clock, look at the data sheet. Your combined task needs to sample at at one of the allowed DSA rates and not exceed the max aggregate rate for the 9204, which in this case ~34kSa/s.

For your other issue, your really need to show your code preferable backsaved to an earlier version.