Minimum pulse width of the PCIe-6361 (X-series) for input counter

[pieleric]

Hi,

We are using a PCIe-6361 DAQ board for measurements of pulses. So far, our equipment generates pulses with a width of ~30ns. Using the PFI input, and counter input for counting edges (on a rising edge), this works fine.

We are now considering a different equipment, which is specified to generate pulses of width 10ns. It seems the base clock of the board is at 100MHz, but I can't find any clear specification on the minimum pulse width for edge counting. Assuming each pulse is spaced "sufficiently" (eg, more than 20ns between each pulse), will the DAQ board be able to detect the pulses?

Cheers,

Éric

[Kevin_Price]

I don't have a definitive answer, but I would tend to be wary.  The specs show a limit for an "external base clock" at 25 MHz, a.k.a. 40 nanosec period.  I can recall from some prior conversation here with an internal NI person that the older 6602 supported higher external clock frequencies than the newer X-series (63xx) due to the nature of their input circuitry.

Whatever exactly causes them to put a spec limit at 25 MHz would give me pause for trying to catch edges of a signal that may come in at up to 50 MHz.   (You mentioned "at least 20 nanosec").

Again, dunno for sure, just a note of caution with a little hint of rationale.

-Kevin P