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NI HW capable of independent HW timed AO tasks

I am aware of the fact that on e.g. one of my USB 6343 X series devices, I can have for AO channels in a single HW timed AO task.

 

That is nice for most applications but sometimes I would like to have two single channel tasks that are both HW timed but reside on the same device.

 

I seem to be unable to find out if such NI hardware exists and if so, which it might be.

 

I might be overlooking something but I am sure NI staff would have the definitive answer.

 

Thanks,

 

Kris

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Hi Kris,

 

Unfortunately this is impossible to do, because in order to have two single channel tasks that are both hardware timed, you would need to have two separate clocks on the same device. This would be possible however on a comapct DAQ, as each module within the comapct DAQ has it's own clock. If you need more information on this, call your local NI office and they should be able to help you.

 

Thank you,

 

Cody

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Hi Kris, 

 

As stated in the above message, the cDAQ has a seperate clock for each module but this still only allows for 1 hardware timed AO task for each chasis (Details of the possible task allocations of cDAQ can be found here:  <https://www.ni.com/en/support/documentation/supplemental/18/number-of-concurrent-tasks-on-a-compactd...

However there are a few modules which do have multiple timing engines, and therefore allow for multiple hardware timed tasks. From the original question I understand that you are wanting the ability for multiple AO tasks, but I have included other possibilties in case. 

 

  • NI 4463 (available for PXI and PCIe) has two timing engines for analog output. 
  • NI 6533 and 6534 devices provide two timing engines for digital I/O.
  • NI cDAQ-9138, 9139, 9174, 9178, 9184, and 9188 chassis provide three timing engines for analog input. The NI 4339 and 4464 (available for PXI and PCIe) also have multiple timing engines. 

If none of these fit the application I can also recomend having two cDAQ chassis and synchronising the tasks. As above if you would like to discuss these option further please let me know and I can put you in touch with your local NI representative. 

Rebecca
NI Applications Engineer

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Dear Cody and Rebecca,

 

Thank you for your answers.

 

Although I understand the resaons for things being as they are, your feedback already confirmed what I initially feared.

 

I have multiple USB 6343 units so for the time being I can just as well link some of them together and drive each AO signal on it's dedicated device. It might not be elegant but it will work.

 

In the future however, I might be better off with some form of FPGA system then? Am I correct in this assumption?

 

My aim is to drive a 2-axis galvo (mirror scanning) system in conjunction with a third focusing unit (a Z-axis if you will). This requires AO at moderate speeds (probably below 1 MHz).

 

Being able to have a device that can handle 3 independent but fully HW timed AO tasks would allow me to have in phase AO tasks which have different periodicity, e.g. If I want to scan a 1024x1024 image on X and Y but create a 5 image "stack" of frames at different Z-position. For the first task I would need to generate more samples than for the Z task (which would only have 5).

 

Another thing I need to be able to do but which I cannot with current hardware is the following:

 

Have a continuous AO task where, between iterations of the sample buffer, the output receives a fixed increment, without software intervention... a new software based write to my task is definietely not an option.

 

This is important since when scanning an XY image, the X mirror will always start a new line at the same (zero) position. Therefore, the X waveform can repeat indefinitely.

 

However, the "slow" Y axis needs to monotonically increase over time. So each period is offset from the previous one.

 

Right now I perform XY scans by providing discrete X and Y samples for the full frame but this is inefficient. It would be much easier to only calculate points for one scanline and output that multiple times (but with a Y offset).

 

X single period

 

Y single period

 

Combined:

 

Combined single period

 

Best regards,

 

Kris

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Hi Kris, 


Is there a specific reason that you need seperate hardware timing for each of these tasks? Most devices support performing one or more software-timed tasks simultaneously with one hardware-timed task to allow the device to generate different signals with different timing characteristics at the same time on the same device. It is also possible to get these AO's to write to the DAC's simultaneously, if sequential updates would cause issues. 


Example of one non-clocked (software timed) task and one clocked task running in parallel: http://www.ni.com/example/25354/en/ 

Example of simultaneous analog output on multiple channels: http://www.ni.com/example/25915/en/ 

 

These options would allow the possibility of incrementing both the x and y axis outputs at different specific rates within the same write function. You can look through both forums and the example finders for previous xy scanning programs. As with AO the hardware is relying on the software program for its latest value update, it wouldn't be possible to vary the AO without software.

 

Also with a little further research, I've found it is possible to have multiple tasks on the same device if there is only ever one task is in the reserved state (like multiplexing) using the DAQmx Control Task VI. It may be useful to look into this example: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000PA7XSAW&l=en-US

 

Let me know how you get on!

Rebecca
NI Applications Engineer

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Hello Rebecca,

 

It is indeed necessary to have HW timing for all tasks involved as I am working on a high speed raster scanner for my microscope where the raster scan itself needs to be synced with a lot of other hardware.

 

I am very familiar with all possible workarounds but it just strikes me as very odd that there would not be any hardware by NI that would be able to apply a fixed voltage offset upon each iteration of a fixed length AO output buffer.

 

Best regards,

 

Kris

 

 

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