PCIe-6323 lock pll and derived sample rate

[TheKr1S]

I have bought a PCIe-6323 with the idea to use it as a synchronous serial transmitter. The challenge is to get is synchronized with a PPS from a GPS. I had the idea I could use the 10 MHz reference clock from the GPS to lock the onboard PLL to. Then derive the sample rate from the PLL to be sure to get the sample rate in phase with the PPS. I expect is can be done, but I can't figure out how.

So in short I expect the clock path would be something like:

GPS --> 10MHz --> /Dev1/PFIx --> PLL --> 100MHz timebase --> sample clock (eg. 128k samp/sec)

This is to achieve that every 128000th sample ends exactly on the PPS

Note: I'm running linux and using the NI-DAQmx C api. Can please someone tell me if this is feasable, and how it's done...

[Kevin_Price]

I've done quite a bit of *direct* syncing of tasks but haven't really explored syncing via reference clock.

Here's an article where section 5 appears likely relevant.  It was written for M-series, but I'd be quite surprised if the same capability wasn't supported the same way for your newer X-series board.

You'd probably need put the GPS 10 MHz clock onto a PFI pin.  Then you'd need to configure your DAQ task(s) to wire the terminal name (syntax will be similar to "/Dev1/PFI4") for that pin into "RefClk.Src".  Because the signal is external to the DAQ device, you'll also need to wire in 10e6 as "RefClk.Rate".

- Kevin P

[TheKr1S]

Kevin,

Thank you for your help, I hope you can help me a little further. I had already found that article, and the clocking image made me expect my solution is feasible.

I already created a program containing:

DAQmxCfgSampClkTiming(h,"/Dev1/PFI4",10000000,DAQmx_Val_Rising,DAQmx_Val_ContSamps,1000000));

But then I end up with an unsupported sample rate of 10e6, the card supports a max sample rate of 1e6. The spec of the card says that the output of the PLL is used input of the 100MHz timebase (as I understand it). Bu then how can I use the derived timebase as input for generating 128k samp/s?

[Kevin_Price]

I don't know the text language API into DAQmx, only the LabVIEW one.  I don't exactly have an answer but here are two points:

1.  Your code appears to be directly configuring a Sample Clock.  The linked LabVIEW code pic is configuring the board's "Reference Clock".  It uses a distinct parameter-setting function that's different from what it uses to configure a Sample Clock.  So I suspect you need to find and use a different API function too, maybe it'll be called something like DAQmxCfgRefClkTiming but that's only a guess.

   The table you posted suggested that the board will only support a 10 MHz or 20 MHz clock signal as its Reference Clock, and that the board can phase-lock its internal 100 MHz timebase to it.  (And furthermore, all internally-generated sample clocks are derived by dividing down the 100 MHz timebase).

2. A slightly different technique I *have* used is to configure a Sample Clock *Timebase*.  Again, I have no idea what the text syntax will be.  In LabVIEW, I could tell DAQmx to use a particular terminal (such as "/Dev1/PFI4") as the Sample Clock Timebase Source.  It could be a 10 MHz signal.  Then I'd separately configure the actual Sample Clock itself, which could then be defined for a rate <= 1 MHz that the board is capable of supporting.

Note: you won't be able to support exactly 128 kHz, only integer divisors of the timebase you use.  If you configure the GPS as a Ref Clock, your timebase is the internal 100 MHz and the desired (but impossible) divisor is 781.25.  I don't remember the rounding rules DAQmx uses, but you'll end up with an integer divisor of either 781 or 782, implying sample rates of either ~128041 or ~127877.   If you configure the GPS as a Sample Clock Timebase, your integer divisor will be either 78 or 79 for sample rates of either ~128205 or ~126582.

-Kevin P

[TheKr1S]

Kevin,

Thank you, you helped me a lot!

I have to use DAQmxSetRefClkSrc() and DAQmxSetRefClkRate() to set te source to /Dev1/PFI4 and the rate to 1000000.

And you are right about the sample rate not possible via a divisor.As a solution I use a sample rate of 1e6. I will generate a bit-rate of exact 38400, not 128000. 1000000/38400 = 26.041111, meaning most bits are generated via 26 samples, and some bits will have 27 samples. having a jitter of 1us does not appear to be a problem.

It is working! Clocks are in sync now!

Thanks!