Pattern I-O Generation with a PXI-6733

[Nave]

Hello. I have a question regarding the time needed to download all the points of a waveform to a PXI-6733. Also wondering when the download and conversion occurs.

In my setup all three cards were using pattern I/O generation and the same external clock and start trigger signals. Originally I would arm the task for all three cards and I noticed the PXI-6733 did not start at the same falling edge of the start trigger as the two PXI-6533s. I'll mention the two PXI-6533s consistently started shifting data together. I figured the PXI-6733 was just slow, so I replaced the external start trigger signal to all boards with a PXI-6602 clock single pulse generated output that I could delay and synch with the original start signal. This worked fine when I delayed the start trigger singal to 1 sec after I all three tasks are armed and started. However, recently we went up to full scale voltage with the PXI-6733 at 10V and I received the following error:

Error -200018 occurred at Property Node DAQmx Task (arg 1) in DAQmx Is Task Done.vi:1->Server Control.vi

Possible reason(s):

Measurements: DAC conversion attempted before data to be converted was available.

Decrease the output frequency to increase the period between DAC conversions, or reduce the size of your output buffer in order to write data more often. If you are using an external clock, check  your signal for the presence of noise or glitches.

Task Name: _unnamedTask<25>

Not sure if the voltage level is related to the problem. Also not sure if this is related but I increased my start signal delay and the problem went away. I'll mention that I wrote the data to the buffer way before I even started / armed the task. So, I'm curious if this delay is because the PXI-6733 needs alot of time to convert data and if it's converting the entire buffer when I start / arm the task. My waveforms can get rather large in size.

[Nave]

I guess a simpler way to ask my question is:

Does the PXI-6733 wait to start converting waveform data till the task is started/ armed?

Is it converting the entire waveform or just the next data point with each clock edge?

Is a 5 second delay from the time the tasks is started / armed till the point the start trigger is sent a relevant fix for my error message?

Should I just write some software to adjust my time delay based on the size of my waveform?

[ManLongAtNI]

Hello Nave,

Does the PXI-6733 wait to start converting waveform data till the task is started/armed?

   Yes

Is it converting the entire waveform or just the next data point with each clock edge?

   Each Data Point is writtne on each clock edge

Is a 5 second delay from the time the tasks is started / armed till the point the start trigger is sent a relevant fix for my error message?

Should I just write some software to adjust my time delay based on the size of my waveform?

   5 seconds seems to be a large amount of time, any delay is a reasonable expectation to allow time for appropriate generation. Howlargee is your buffer, can you post some code?

[Nave]

Thanks for the reply. I see that each data point is written on each clock edge. However, when does the data conversion occur? Is each data point converted from a digital code to an analog level just prior to the data point being shifted out; or is the whole buffer converted once I arm the task? My board is past due for calibration; so I went ahead and sent it out just to be safe. I can't post any code, but I can post print windows.

I create all my tasks in DAQ-Setup.pdf

The relevant 6733 tasks is the first VI to receive the error cluster input  - DAQ-SES Voltage Setup.pdf

My waveforms typically contains ~130,000 points

Server Control.pdf is the main server-side application. On page 1 in the bottom loop I start/arm the 3 pattern generation tasks inside the sequence structure. Then I have a 5 sec delay and start my synchronized start trigger.

[ManLongAtNI]

I was able to get the following information from the Manual

 

The DAC reads a sample from the FIFO with every cycle of the AO Sample Clock signal and generates the AO voltage

Hope that answers your question

[Nave]

Hi. I'm back. I found a link describing this FIFO you speak of:

http://digital.ni.com/public.nsf/websearch/CC07E585D9F94D2B86256C1A005344EF?OpenDocument

I read the datasheet on my PXI-6733 and it says the FIFO buffer is 16,384 bytes for my 8 channels. My waveforms are typically 72kB in size and I output on 1 channel.

According to the document in the link I'm in Non-FIFO mode! Is it ture that for FIFO mode all of the waveform has to fit in the buffer or it defaults to Non-FIFO mode?

If so, I'm wondering if its possible to setup the card to use FIFO mode with a very large buffer. I'm thinking I would need to turn on allow data regeneration and keep writting memory to keep the buffer full. I could probably devise a way to track how much of my waveform I've written, but I don't see a way to determine how much data is currently in the buffer.

If not, I think the system is falling behind in time when it goes to grab the next section of waveform to transfer. Is there another Analog Output Card with a butt load of FIFO memory and 8 DI lines and 1 AO line.

[ManLongAtNI]

Hello Nave,

Keep in mind the FIFO setting you're referencing is defined in the Traditional DAQ driver. The DAQmx driver uses a property node that can be found Analog Output:GeneralProperties:Advanced:Data Transfer and Memory:Use Only Onboard Memory Property. Similar to FIFO setting, it's default setting is false  where the analog output buffer resides in PC memory. You are unable to increase the size of your FIFO buffer in software since this is a hardware limitation.

If you are looking for large onboard memory I recommend looking into FGENs and HSDIO devices. I can have a National Instruments employee contact you to discuss your application and provide feedback if your application is achievable with your current hardware. Just reply to this post identifying you would like to be contacted for this reason and I can have a representative follow up with you. 

[Nave]

O.K. I found the problem, upgrading or changing my hardware won't be necessary; but thanks for the help.

Looks like the problem was DB loss from my fiber optic clock signal. I had 5 fiber optic patches in the signal and it appears to be 1 too many. I stumbled on this problem when one of my Pattern Generation I/O 6533 cards bombed out just like the analog card had been. I removed 1 patch in the signal path and no more errors. It didn't occur to me that the light signal could be cutting in and out. I just figured with DB loss it would just miss pulses completely.