Retriggerable output plus staircase voltage update at every retrigger

[Vectrix]

Hi,

I set up a retriggerable output according to the method described in

http://zone.ni.com/devzone/cda/epd/p/id/4787

I am using PXI6259 with LabVIEW 2009 SP1 on Windows 7 x64 platform.

I am trying to update the voltage discretely on a separate analog channel, say ao1, every time the ctr1 outputs, which is precisely the same time as the first output, ao0, is retriggered.

I have tried using several methods to solve this problem. One was using a timed-loop using "DAQmx create timing source" vi. However the vi requires an additional counter to work with digital edge with counter, but there is no more to spare since the retriggerable setup takes up two counters already. I also tried connecting counter output event into signal from task and hook up the counter channel from the retriggerable setup, but that uses the ctr0 output and not the ctr1 output as the timing source.

Is there a way to use ctr1 internal output as a timing source for the timed-loop? maybe through some re-routining using "DAQmx connect terminals.vi"? I tried this too without any luck, but I think I might just be connecting the wrong connections.

Many thanks in advance.

[Eric_L]

Hello Vectrix,

From your description, it sounds like you want to output the same waveform repeatedly and have an analog voltage which indicates the number of repetitions, is this correct? If this is the case, what is the target update rate and time between retriggering?

Eric

[Vectrix]

Thanks for your reply.

And yes, that is correct. The key thing is that the waveform is retriggerable, and I need to count the number of times it is retriggered. I'm not 100% certain that you mean by the target update rate, but the retriggering rate is from 70 to 250 Hz.

[Eric_L]

Hello Vectrix,

I was a bit unclear with my question about target update rates. Let me clarify the question. The two rates I was asking about are as follows

1.       What is the sample rate that the AO is writing out (or what is the frequency of the pulse train that is used for the AO sample clock)?

2.       How often do you retrigger the AO task? (70-250Hz from your last post)

Another important piece of information that may be relevant to this application would be the number of samples in the waveform.

If you waveform is small enough, you would be able to load multiple repeated signals of the repeated waveform and load a matching number of points for the counter output (analog voltage). The regenerated pulse task would control the output of these points, but the analog voltage for the count would need to be updated before all the count voltages are depleted from the buffer.

Since both output channels have to use the same timing mechanism it makes updating the single output difficult. Depending on the specifications of your application, we may be able to devise another solution.

Eric

[Vectrix]

Hi Eric,

Thanks for clarifying.

Let me add more details here to help with the understanding of my answer.

I want to drive a two axis translation stage using the two waveform, one waveform (triangle) for fast scan and the other for slow scan (step voltage update), forming a raster scanning pattern. The start of each fast scan needs to be synced with a data acquisition (DAQ) system which outputs a TTL trigger at > 36 kHz.

Now to answer your questions,

1. The sampling rate changes depending on the desired frequency of the fast scan. For ease of discussion, let's use a fix frequency of 70 Hz, which, from my vi, gives a sampling rate of 70 kHz using 1000 samples per cycle and 1 cycle per buffer setup. Notice how this frequency is much slower than the triggering rate, so the vi simply ignore the triggers during waveform generation and only waits for trigger again when it finishes outputting the buffer.
2. The TTL trigger is actually > 36 kHz, but the actually retriggering is limited by the "fast scan" waveform at 70 Hz.

Correct me if I am wrong, in your 2nd last paragraph, are you suggesting to load multiple cycles of the fast scan waveform into the buffer and output that instead? This is not ideal since the beginning of cycles other than the 1st are not guaranteed to be synced with the TTL trigger, which is a hard requirement for my application.

As I mentioned in my original post, I can see the output from ctr1 on the scope and is exactly what I want to use as a timing source for a timed-loop and simply update the voltage everytime the timed-loop is awaken normally. Is there any way to make this happen?

Nonetheless, I welcome all suggestions, and greatly appreciate your time and effort.

Many thanks,

V

[Eric_L]

Hello Vectrix,

You would have to load 2 matching length wave forms for each channel. The output will be controlled by the pulse generation task, which would all maintain alignment of the 2 channels of data.

For example

0123210  0123210  0123210  (Repeated Waveform Data)

1111111  2222222  3333333  (Slow Voltage Step Data)

The finite retriggerable pulse generation task would generate 7 clock edges each time it is triggered. Each time it is triggered, the analog output will output a group of triangle waveforms along with the matching analog voltage level. Time intervals between triggers (and after the 7 outputted AO values) will result in no clock edge allowing the analog output to hold the last value written.

At the moment this is the only method I can come up with to update a single channel and maintain the same waveform for the other channel. I will talk to other engineers to see if they have any additional solutions.

Eric

[Vectrix]

Hi Eric,

But when do I update the buffer on the slow voltage step channel? From the retriggerable AO sample code, the data is written to the channel and a while loop is called to keep the vi running.

Thanks very much for your help,

V

[Eric_L]

Hello Vectrix,

Can you clarify your last post or post some example code to the forum?

Eric