SPI communications with X-series DAQmx and SDW (maximum speeds)

[cbutcher]

I'm looking for a little help/confirmation/clarification on the specifications of the USB-6356 (or similar X-series multifunction DAQ devices).

I want to use the SDW library to communicate over SPI at a higher speed than I have previously (before, my SCLK was only O(100kHz)). The specifications of the USB-6356 device, taken from the datasheet, are as follows (perhaps I picked the wrong 'relevant' parameters):

DI Sample Clock frequency : 0 to 1 MHz system and bus activity dependent

DO Sample Clock frequency

From FIFO : 0 to 10MHz

Streaming from memory : 0 to 1MHz, system and bus activity dependent

Waveform generation (DO)

FIFO : 2,047 samples

Counter Internal base clocks : 100 MHz, 20 MHz, 100 kHz

Frequency Generator

Number of channels : 1

Base clocks : 20 MHz, 10 MHz, 100 kHz

Divisors : 1 to 16

Output to any PFI terminal

The SDW library works by (as I understand it) using a sample clock at a higher rate (pulse generation from a counter) to time digital inputs and outputs, including the SPI's 'SCLK' line (the clock for the reads and writes). This is so offsets between each line can be timed more precisely (i.e. fractional parts of the SCLK line.

When I previously used this, I didn't need such high output rates, so I didn't worry so much. Now, I want to check:

• My counter output, for timing the inputs and outputs, needs to be perhaps 10 times faster than SCLK
• If I want to run my SCLK at perhaps 1MHz, my counter output should be around 10MHz. This should be fine, since I have a 20MHz base clock I can use - I can use that with no divider and then either speed up or slow down the SCLK to use more or fewer than ~20 pulses per pulse period of SCLK, or I can use the 10MHz, or I can use a divided 20MHz.
• However, my digital inputs and outputs can only run, as I read it, at a maximum of 1MHz. Whilst I *think* I can make the outputs regenerate and so alleviate the problem there (10MHz max) I don't know that I can do anything with the digital inputs. I only need to read on one edge of the SCLK pulse, but can I have a DAQmx task triggered by a pulse train an order of magnitude faster? If not, will I need to connect the digital output (SCLK) for use as a sample clock for the digital inputs and outputs?
• When I previously did this, I wrote 10 true values for a high, and 10 false for a low, and when reading inputs I decimated the array that DAQmx read by a factor of 10. Is avoiding this by using the digital output as a sample clock a better choice?
• If I wanted to have faster communications, what would be the recommended hardware?

Thanks for any suggestions, tips or clarifications. Apologies for any misunderstandings on my part.

[crossrulz]

Personally, I would use a device that was specifically made for SPI.  The USB-8452 claims to go up to 50MHz for the SPI bus.

I do wish NI would make a PXI and PCI version of that board.  I do I2C testing a lot.

[Kevin_Price]

I was surprised at the limited bandwidth of 1 MHz you reported -- until reading again a little closer and picking up on the USB part of the board name.  That extra limitation is one of the reasons I carry a bias in favor of desktop bus-based cards whenever feasible.  If you can set up this app around a PCIe desktop X-series board, *run* don't walk and do it.

X-series hardware and timing capabilities will likely support the 1 MHz SCLK scheme you're after.  The PCIe bus would as well whereas you *may* run into trouble with USB, working right at spec limit.

You can configure sample rates on the X-series board in terms of a timebase clock signal and an integer timebase divisor.  I've never really used the frequency generator feature and am not 100% sure it can be routed to be used as such a timebase.   I'm also not sure if it can be stopped & started nor whether the start can be triggered.  But I *am* sure a counter output task can do all these things and can also run at the desired 10 MHz (or 20).  So there will be options.

This would be better than a scheme that counts on 10x (or 20x) decimation due to all the extra wasted data bandwidth over the bus.

The remaining thing to consider is *phase*.  Maybe this doesn't matter for you, but if it does you'll want to control or at least know where within each set of 10 (or 20) freq clocks does the active edge of the SCLK occur?  I don't know this for sure but my best guess is that the timebase divisor approach will probably try to make a square wave, i.e., SCLK edges at freq clock #5 and #10 (or else #10 and #20).  If you need control over the phase, there are ways.

All that being said, you'll probably be better off if you can use a dedicated board for the purpose as crossrulz already recommended.  I've been addressing the "can I?" part of your X-series question, he's addressing the more important "should I?" part.

-Kevin P