Sync Multiple cDAQ

[GregAA]

Hello All,

I am working on the theory for an application that would involve multiple cDAQ chassis where synchronization between AI channels is important.  My thoughts on how to accomplish this are as follows:

-Identify one AI module as the “master”.

-Setup the Sample clock for this module such that it is routed to the PFI0 output using a DAQmx Export Signal property node.

-Setup this module’s timing such that it uses the internal sample clock, which will be set at 10kHz for this application.

-Wire the PFI0 terminal from the master module to the other modules’ PFI0 terminals.

-Setup all remaining modules’ timing such that they will use the PFI0 input as the sample clock.

-All channels will be setup for continuous acquisition.

-Start the DAQ for all slave modules (via a software trigger).

-Start the DAQ for the master module (via a software trigger).

-Collect data.

My understanding is that the data I would collect as a result of this method would be completely synchronized such that each element of the resulting arrays would represent a sample at the same time for any corresponding element of a different channel’s array (within the jitter introduced by the convert clock).  Thus I should be able to achieve a +/-100uS timebase accuracy when using a 10kHz sample clock.  I would assume using a software start trigger is ok since the slave modules will simply sit and wait for the clock signal to appear when the master starts?

Does my reasoning sound accurate?  Are there any major components I am overlooking?  As I said, this is just theory at this point- so no code to post yet.

I’ve only used PCI-DAQ devices in the past- so I’m new to the cDAQ model.  Is there a single SampleClock for the entire chassis, or does each AI module have its own?  I haven’t been able to find a clear answer from the documentation I’ve read so far.  Likewise, what is the difference between the PFI BNC connectors on the cDAQ-9188 chassis verses the pins on the NI-9205 module? (As an example)

What would be the maximum distance between chassis where such a scheme would work reliably?

Thanks for your help,

Greg

[REDS]

 Hello Greg,

Thanks for posting in the Discussion Forums! A good piece of literature for you would be the Synchronization Explained white paper. It lists all of the synchronization methods for you.

As for synchronizing cDAQ chassis, the best option you have is to share your Sample Clock among the cDAQ chassis.

-Identify one AI module as the “master”. Correct.

-Setup the Sample clock for this module such that it is routed to the PFI0 output using a DAQmx Export Signal property node. Correct.

-Setup this module’s timing such that it uses the internal sample clock, which will be set at 10kHz for this application. Correct.

-Wire the PFI0 terminal from the master module to the other modules’ PFI0 terminals. Correct, you can choose any PFI line to import  / export your sample clock.

-Setup all remaining modules’ timing such that they will use the PFI0 input as the sample clock. Correct.

-All channels will be setup for continuous acquisition. Correct.

-Start the AI task DAQ for all slave modules (via a software trigger). Correct.

-Start the AI task DAQ for the master module (via a software trigger). Correct.

-As Master task starts, the “ai Start trigger” line automatically goes high.

-Slave task starts acquiring as soon as it receives the “ai Start Strigger” and it receives the (rising of falling) edge of the sample clock.

-Both tasks collect data.

The cDAQ is fairly similar to your PCI DAQ card as to the code, with the difference that some PCI cards have access to Reference clock synchronization, which is a better way of synchronization than to just share the sample clock and start trigger.

The sample clock is provided by the chassis. cDAQs have three analog input timing engines at your disposal (including the 9188 that is not listed in the KB, I will update it). This means that you can specify three totally different sampling rates per module. You will still have the limitation of just one task per module (unless you are using counters).

The maximum distance will depend on how much the signal attenuates and skews. Apparently, you could get up to 25 – 50 ns skew over a 100 m twisted pair copper cable. Regarding attenuation, it will depend on the impedance of the cable, which is a function of the length and the frequency due to the skin effect. There are pages that could help you calculate the attenuation of your specific cable.

[GregAA]

Hi Daniel, thanks for your response.

Two questions:

1- Will it be possible to view the SampleClock signal on a scope if I connect it to the appropriate PFI line?  Will there be any special signal conditioning required, or will a high impedance scope probe be sufficient?

2- Is the hardware Start Trigger necessary?  Would it be possible to start the DAQ using a software trigger and then just rely on the first edge of the sample clock syncing the first sample with the other chassis?  If not, can you provide more information about the Start Trigger VI you show above?

Thanks Again,

Greg

[REDS]

Hi Greg,

1-      Seeing the simple clock with a scope should be really straight forward and I don’t expect any signal conditioning required.

2-      Because you are sharing the sample clock, I don’t expect the start trigger to be absolutely necessary as you want the acquisition to begin right away. (You aren’t waiting for an external signal to trigger the acquisition, are you?) I remember doing sample clock synchronization with a couple of devices and the start trigger didn’t seem to make a difference, so the software start trigger won’t be necessary.

[GregAA]

Thanks Again,

1- That's what I thought.  I mocked up a simple system using PCI boards- yet I can't seem to display the clock signal on the scope.  I've confirmed that the PFI channel is functioning properly by testing it in a static Dig Out mode.  Do you know what levels I should expect to see for the clock signal (5v TTL, etc)?

2- I assume you meant to say "the hardware start trigger won't be necessary" above?

[REDS]

Hi Greg,

1-      Can you wire the PFI line that has the sample clock output to any AI channel and see the sample clock? If you don’t, what are the exact connections that you are making? Please mention pin number and module / PCI card.

2-      Correct. The hardware start trigger won’t be necessary.