USB-6251 Capabilities

[Brian Bean]

A couple of questions regarding the USB-6251.

1) If you configure a USB6251 to use PFI Ports 1 and 2 as CTR/Timers does that eliminate the unused lines on those ports (P1.5,1.6,1.7 etc) for use as static digital I/O channels.  I guess my question is if I configured as I mentioned above does that mean I only have 8 (P0.<0..7> ) digital lines available for other input and outputs.

2) The CTR application we are trying to pair the 6251 with requires counting 30 ns pulses over a period of 1 min.  Will this be possible if we integrate the counts over 1 sec periods?

The application we have may require up to 9 digital output lines, 8 digital input lines, 2 ctrs, 2 AI, and 2 AOs

[dansch]

Hello Brian,

To answer your questions,

1.)  Each PFI terminal can be individually configured for Timing I/O or static Digital I/O. Depending on the type of counter measurement you are trying to perform, the counter may require multiple PFI lines. If any of these lines are used by the counter, you cannot use them for Digital I/O. However, just because certain PFI lines are used for counter input/output, this would not eliminate the use of the other open PFI lines (P1.x lines) for static Digital I/O.

2.) I am slightly unsure what you mean when you say you want to “integrate the counts over 1 sec periods”. Do you mean that you want to take the count every 1 second, such as in buffered edge counting? For the 6251, the minimum input pulse width is 12.5ns, so if 30ns is your pulse width, then you should be able to count the pulse.

Hope this helps,

[Brian Bean]

Thanks for answering my questions.

So if I have two buffered counter inputs would I use up 2 PFI lines for each CTR timer input (SRC & GATE, ) for a total of 4 used PFI lines for my CTR Task?

Any suggestions for providing the GATE signal from the same device?  Can I simulate a TTL signal with an analog output and physically wire it to each of the CTR's gate terminals since my CTR sampling freq is so low (1 per sec).

thanks again.

[dansch]

Hi Brian,

You are correct in that you would need two PFI lines for each counter task if doing buffered counting. Thus, you would need 4 lines total if using both counters. For the gate (sample clock source) of the counters, you could use an external source from another PFI line or a sample clock from another task. For instance, you could use the analog input sample clock. Because your application is requiring so many other tasks, such as analog input, analog output, and digital I/O, it may be difficult to find a dedicated source to use as your gate. You could try to use a digital output, but I am not sure how many lines you have available and if your digital line you have available would be static (software timed) or correlated. Using something such as an analog output would work, though it may be complicated to reproduce the exact signal you need if you are already using your analog output sample clock for another analog output channel. As I was saying earlier, you could use one of the sample clocks and this would simply require that you decimate the data in software (by just ignoring all the data except the ones that occur a second apart). While any of these methods would work, finding the best way to create your gate signal really depends on what channels you will have available to use. Let me know if you have any further questions regarding any of the options mentioned. Thanks,