Use of external sampling clock slower than minimum specified

[TDP]

For complicated reasons, I'm in the position fo trying to use a PXI-6115 board to do data acquisition at ~2 kS/s using an external sample clock. The board datasheet says minimum sample rate is 20 kS/s.  Is this more a specification on the quality of the internal sample clock at these sampling frequencies (board max rate is 10MS/s), or are there likely to be other problems with the ADC?

[NEWKlear]

TDP,

As the minimum is 20 kS/s the ADC will take that many readings no matter what.  The best thing for your application will be to decimate the data down to your sampling rate.  The Decimate VI will help.  More information on it can be found here:

 http://zone.ni.com/reference/en-XX/help/371361H-01/lvanls/decimatecont/

I hope that helps.

[TDP]

NEWKlear,

Interestingly enough, I seem to have kludged the board into doing acquisition at rate I wanted---duration of sampled data and internal checks tend to confirm this.  But I'm curious whether the data is accurate.  You'll likely say "can't be sure".

The Decimate.vi suggestion is poroblematic...I need synchronous acquisition based on my external sample clock.  Oversampling and a decimation will only work if the internal board clock and the external clock are phase-locked.  I could WAY oversample and then use some more sophisticated winnowing technique, but pre-winnowed data sample would be inconveniently large.

I think real solution is to move to a more appropriate DAQ board.  I've been working that angle, too and may be able to work on a MIO-16E board, if I can resolve some computer issues.  And if this dinosaur of a board still works.

Thanks.

TDP

[NEWKlear]

TDP,

one thing to be aware of is that the synchronization is all done on the board itself, then the data is transferred to the PC where you can decimate the data to the desired sample rate.  So decimating the data will not affect your synchronization.

I hope that helps,