Hi，
I'm sorry for my poor English，but I really need help。
I used an FPGA to generate an LVCMOS level square wave as the 6733 external clock.
Square wave frequency is 16KHz or 8KHz, connected to PFI0 pin of 6733.
Pin 9 of 6733 DGND is connected to the GND of the FPGA。During the rising and falling edges of the external clock, there is a glitch of about ± 200mv in the voltage output by the 6733。The waveform is measured by PCI-5105 at 60M sampling rate.
