cRIO Complex Timing (AI + Buffered DI + DO train)

[Jed_Davidow]

Howdee all,

I have an application where I need to sample somewhere between 1KHz and 10KHz overall.

For each sample, I will be collecting a couple 16b AI channels (no problem), but at the same time I need to run a complex DI/DO scheme.

The scheme is that I need to produce 24 DO clock pulses at 1MHz every time we sample, and those clock pulses will be used both externally and to drive a DI line to collect data (this is a serial data line).

So bascially, at every 1KHz sample, I need to sample the AI and then generate the 24 pulses + sample one DI line.

Can this be done with a cDAQ 9478 chassis + 9209 + 9411?

Esentially I would set up a 1 or 10kHz counter to be used as both the AI sample clock and a trigger for the DO pulse train; The DO pulse train would then be routed to the sample clock for the single DI pin (and externally).

I suppose the other choice would be to sample the AI with each of the 24 pulses and just ignore the last 23 measurements; if the module is capable of returning data faster than it's collected on cDAQ.

Ideas?

[kkravetz]

Just to clarify, which platform are you using? The title says cRIO and you mention a cDAQ chassis 9478 but I'm not seeing either platform have that number for the chassis.

[Jed_Davidow]

Dammit! cDAQ.

[_kb]

I haven't validated it, but I think you can just set up your digital task(s) as finite and retriggerable, with the AI sample clock as your start trigger.  This would be the timing and triggering configuration for the digital side:

No counter programming necessary.

[Jed_Davidow]

My simulated hardware errored on the Retriggerable setting.

[_kb]

My mistake.  This won't currently work on cDAQ -- only on PCIe/PXIe-63xx.

So, you will have to set up your counter output, but the same triggering configuration (using AI sample clock) on the CO task will be the best way to generate the burst clock you want for your DIO tasks.