Thanks a lot Will,
I was working just in the opposite direction. Now that is clear enough.
By the way, there�s something else I�ve found in this application note that I can�t understand. Don�t worry; this is the last one 🙂
In page 6 under the �Resolution, precision and accuracy� discussion, it is said that an ideal 24 bits ADC would provide up to 7 digits resolution, an 18 bits 5 digits and an 18.6 bits 5 1/2 digits. How is this derived?
I�ve tried reasoning it, but I don�t get the same results: a 24 bits ADC can count 16 777 216 steps, which means from � 8 388 608 to + 8 388 608. This would be a 6 �and something� digits, almost 7 digits. With the same reasoning I get +/- 131 072 counts for 18 bits and +/- 198 668 counts for 18,6 bits. Why one i
s 5 digits and the other 5 ½ digits?
Then I try the other way:
- A 7 digits DMM can count +/- 9 999 999 = 19 999 998 steps.
This would require and ADC with 25 bits at least (2^24=16 777 216 steps, not enough)
- A 5 digits DMM can count +/- 99 999 = 199 998 steps.
This would require and ADC with 18 bits at least
- A 5 1/2 digits DMM can count +/- 199 999 = 399 998 steps.
This would require and ADC with 19 digits at least
Thanks a lot again.
PS: by the way, I think this is one of the best and most valuable application notes I�ve ever found about these topics. There�s not much around, and it�s a really important matter.