I have a need to read 50 analog channels (of aproximately 100 mv). The signals are time multiplexed through 50 "1-of-3" switches.
(Basically the 1-of-3 switch is just 3 FETs, with one of them on and the other 2 off).
For 1/3 of the time the signal comes through "FET A", then through "FET B", then throuhg "FET C".
In this way I am actually reading 150 signals.
Additionally, half of the time the signals are "live" and half the time they are shorted into a dummy load. This is done to help remove noise.
So I actually have 300 signals.
I plan to use the 6255 card in single ended mode to read the signals.
I also want to use 3 digital I/O lines to sequence the FETs, and a 4th I/O line to toggle from "live" to "dummy load".
(I could also just output a pulse train, and use external logic circuit to generate the pattern if necessary)
So, the pattern on the 4 I/O lines would go something like this: 0001, 0010, 0100, 1001, 1010, 1100..... and repeat.
The MSB is the "live/load" line. Bits 0, 1, and 2 turn on one of the FETs in the "1-of-3" mux.
I want 3600 updates per second of this 4-bit value. (So, if using external curcuitry I would drive it with a 3600 Hz pulse train).
The problem is how to synchronize the analog input with the mux (and optionally vary the sample rate of the analog while maintaining the 3600 Hz switch rate).
When the pattern is 0001, the signal on DEV1/ai0 belongs in "bucket A0".
When the pattern is 0001, the signal on DEV1/ai1 belongs in "bucket A1".
When the pattern is 0001, the signal on DEV1/ai2 belongs in "bucket A2".
When the pattern is 0001, the signal on DEV1/ai3 belongs in "bucket A3".
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.
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When the pattern is 0010, the signal on DEV1/ai0 belongs in "bucket B0".
When the pattern is 0010, the signal on DEV1/ai1 belongs in "bucket B1".
When the pattern is 0010, the signal on DEV1/ai2 belongs in "bucket B2".
When the pattern is 0010, the signal on DEV1/ai3 belongs in "bucket B3".
When the pattern is 0100, the signal on DEV1/ai0 belongs in "bucket C0".
When the pattern is 0100, the signal on DEV1/ai1 belongs in "bucket C1".
When the pattern is 0100, the signal on DEV1/ai2 belongs in "bucket C2".
When the pattern is 0100, the signal on DEV1/ai3 belongs in "bucket C3".
These patterns continue up through DEV/ai24 and "buckets" A24, B24 and C24.
Additionally, when the MSB in the digital pattern is 1, the "bucket" changes to "bucket A0 background" for example.
This works out to 300 signals I'm trying to capture. I want to be able read the digital pattern on bits D0 - D3 and
use that to determine which bucket to put the signal in. But I want to do it with "hardware" rather than "software" reads.
My intial thought was to trigger on a digital pattern, but that would only ensure the very first sample goes to the right "bucket".
What I'm really looking for is a way to read analog samples and stamp them with the value on bits 0-3 of the digital port. Then
I could use external hardware for the pattern generation and just use the 6255 for input (maybe use ctr0 to drive the external hardware).
Then I can easily sort out which bucket each signal goes into based on the value on the digital lines. My problem is figuring out a way
to do the reads (both analog and digital) and ensure they are synchronized with each other.
Any thoughts would be appreciated.
