COPPER BOTTOM LAYER PROBLEM

[kittmaster]

I ran this following Nestor method and while that does fix the visual part of the equation there is something else seriously wrong.....

I autorouted it, it says 100% complete, and I went back and cleared the results and ran a DRC and nets check....says the design is in full compliance....but look at the device pin 2.....checked the pin for net connection because it isn't dark blue but light blue denoting net connectivity.....umm.......says its connected to net 12...but there is no trace attached to it?????

You can see both layers are enabled, there are no trace on the top layer since I made it none routeable......

I KNOW my MS UB is 100 functional since I've created 30+ complex PCB's with it in the last month.

Figured this was important enough to repost a problem

thoughts?

Chris

Message Edited by kittmaster on 08-01-2007 10:49 PM

[Tien_P]

Hi Chris,

I looked at your board and the connectivity check is correct.  If you select Tools-->Netlist Editor, go to net 12 and click on the "pins" tab, you will notice only 1 pin was assigned to net 12.

Tien

NI EWB Support

[kittmaster]

Tien

I understand and that was one of the first things I looked at when I posted this......what I don't understand why the pin 2 is hightlighted and a net 12 is physically assigned to that pin regardless of what the netlist editor says.

Its a direct contradiction.....which are you supposed to believe????? That is what my confusion is here. I do understand what your saying, but it seems to be completely wrong based on the visual vs. netlisted data information

[nestor-sg]

Lacy, I looked at your file and I know why it is not routing...

Open the first file you posted... "Longwall Timer"... then on the spreadsheet view, go to the nets tab... then scroll right until you see a column named "Routing Layers"... you can see that many nets are assigned to be routed only on Copper Top... is a binary-like selection 10 means Coppert top but no copper bottom... 11 means both... 01 means route only on copper bottom. You can use the shift key and select all rows at once... then click on that cell (routing layers) on any row and make the appropiate selections (only copper bottom should be checked) then click OK and you'll see that now all nets have 01... try routing again, it will almost finish (96%) you might need to move around one or two components to give it space to find routes for the rest of the traces...

[lacy]

Much appreciated Nestor and it did work.Thank you  Could you give me a clue as to why this changed since I don't recall making any changes to the default setup? Also, why iwould the spreadsheet view settings override my PCB settings?  It would seem logical to me that if I changed the main PCB settings that should be reflected in a simular change in the spreadsheet shouldn't it?

[kittmaster]

Nestor

I'm also seeing this behavior as well and its new. I would classify it as a defect.

All of my layers in MS are set to all but when the net list imports (using a dual layer) it is defaulting (only on certain nets....) 10 for the routing layers even though MS says to use both sides.

I have to go in there and set it manually to 11.....this is a new thing to handle when a board doesn't route. I've tried switching MS to top only bottom only, yet UB sets it to 10.....

So I can confirm Lacy's diagnostic as happening here as well.

[lacy]

Thanks Kittmaster. You actually defined the scenario/problem better that I did.

[jja]

Re: COPPER BOTTOM LAYER not longer visible


suddenly the “COPPER BOTTOM LAYER” is not longer visible, it appears instead a “Bottom buildup 1” ( ultiboard 10 )

I have try with a new project, new pcb (creating  it as a 2 sides board using pcb wizard ) , with same results.

But if I open an ultiboard sample, like the “round router”, here the“COPPER BOTTOM LAYER” appears again.

I must have changed a set up parameter somewhere, but I can not find what is it.

Pls help

juan

[lacy]

Check you layer setting under PCB PROPERTIES>COPPER LAYERS and check to make sure the single layer build ups are set to zero. This is the only thing I can think of that might be causing this without looking at your file.

I hope maybe this will help.

[lacy]

I have found something that could be a situation in the software concerning this. It seems to happen when you do a Multilayer board and then close that project and then try to go back to a normal 2 sided board. So I do not believe this is something that you caused. I have the same situation now and I am going to try and fin d a way to get rid of it. I will let you kn ow how to eliminate this once I find iout how to do it myself.

I went into PCB PROPERTIES and unchecked save as default and then closed Ultiboard and re-opened it and all is well again. I could not get it to repeat what it did before.

Message Edited by lacy on 03-27-2008 07:28 PM