D Flip-Flop outoput is not matching clock duty cycle

[ashifulk]

I am using a 7474N generic D Flip-Flop and I would like the output to be at 10% duty cycle. The input clock for the flop-flop is at 10% duty cycle with a 1.4MHz frequency but the output (Q) is at 50% duty cycle. Is there a reason why this is happening and/or am I doing somthing wrong?

Thank You.

[johnsold]

That is the way flip-flops work.  I have been designing circuits since before the 7474 was released and I have never seen a circuit with one flip-flop which could have a 10% duty cycle output.

If you want the output to be the same as the input, just use a wire.

What are you really trying to do? Can you post a timing diagram or logic diagram?

Lynn

[ashifulk]

Oh... I didn't know that actually. Thank you for clearifying it. I'm trying to take a 1.4MHz (8*F0) signal and output 3 signals using a series of D Flip-Flops. The 3 output signals are 175kHz (1*F0), 350kHz with 0 degree phase shift with the 1 and 8 F0 signals (2*F0 w/ 0 degree phase shift) and 350kHz with 90 degree phase shift with the 1 and 8 F0 signals (2*F0 w/ 90 phase shift).

I don't have the circuit daigram I'm using handy right now but I will upload it a little bit later.

[ashifulk]

Sorry I forgot to answer the most important question. The output of the Flip-Flop's is used to drive a sensor circuit and we want to see how the output of the sensor changes as we vary the duty cycle of the clock (the 1.4MHz signal).

[johnsold]

For the signals where you are dividing down from the clock, you can get lower duty cycles than 50%. It should be fairly easy to get 12.5% at F0 and 25% at 2*F0. To get 10% at either of those frequencies is still not easy without a higher frequency clock.

I do not have Multisim.  If you want me to look at your circuit, please post it as a .png image.

Lynn

[ashifulk]

Attached is the circuit.

[johnsold]

This circuit is simple enough that you can generate a timing diagram manually.  I recommend that you do that.

The 2f signals are at 350 kHz and the f signal is at 175 kHz. There is a 90 degree phase shift between the two 2f signals. The f_0 signal is almost in phase with the 2f_0 signal. It is delayed by the propagation delay from clock to Q of U8A. How much that phase shift is in degrees depends on which logic family you choose because the propagation delays are different.  For example the 74C series, which is the slowest CMOS family and has a propagation delay of 180 ns, would result in a phase shift of about 23 degrees.  Faster logic families will have smaller phase shifts.

Lynn