Delay Lines MultiSim

[Sparky44]

Hello All,

Hopefully someone can point me in the right direction.  I am currently building a PLL and am in need of a mechanism to insert a delay in one of my signal paths, but have thus far been unable to figure out how to accomplish this.  Any help is greatly appreciated.

Sparky44

[lacy]

I am going to respond to this in order to push it to the top.

I am not exactly sure as to what would be need here. When I hear about "delay lines" I am thinking in terms of television circuits. They have delay lines in the video section (older models circa 1985-1990) and this is basically just a series coil in line with the video amp. I don't know if this is what you are referring to or not.

Sorry, but I don't think I can be much help in this situation.

[Sparky44]

Lacy,

Thanks for the response.  Bear with me as I am relatively new to MultiSim.  The delay is required to facilitate construction of a phase/frequency detector for use in a Phase Locked Loop.  I have not searched high and low yet for a PLL IC....although I realize there are VCO's with a PLL built in.  Rather, I am building this from scratch.  This particular stage needs a delay to allow both frequency and phase detection.  The catch, I think, is being able to discriminate for both below and above phase v.s. frequency, ultimately being able to develope the appropriate output to drive a VCO to either a higher frequency or lower frequency.  I belive the delay is needed to allow proper detection and prevent excessive phase noise. 

I hope this helps...of course you know what they say the longer you talk(type)...lol...the knowledge or lack there of (meaning me of course) spills forth. 

Thanks for the reply and help!

Sincerely,

Sparky

[Sparky44]

Lacy,

Yup...see...when I talk too much....ha!  The requirement for the delay is to reduce deadband.

[OStep]

Sparky,

You can use a transmission line to model delay. A lossless transmission line is specified as per the following example
 
T1  in1 in2 out1 out2  Z0=75 TD=1e-6

Make sure to match your circuit impedances to Z0 and you should get an ideal delay equal to the value of TD

There's exists a Multisim component for this model under Misc->LOSSLESS_LINE_TYPE1

Regards,

[Sparky44]

Max,

Thanks a bunch!  I figured there was some method to produce a delay.

Sincerely,

Sparky