Design Rule Check Error

[Hallee]

I have a component in my Multisim layout that has a package MINISOIC-10(MUB10A). It is for the audio amplifier LM4667MM. When the Multisim circuit is transferred to Ultiboard and the autoroute option is used it gives the error that nets are too close together. When finding these nets I find that it does not like how close the pins are from the component and therefore cannont find a route for the trace. I know this is the correct package so how do I get Ultiboard to realize the spacing between the nets for the pins cannot be changed.

[Tien_P]

Hi Hallee,

There is not much you can do about the pin locations and often sizes, if the pin default settings resulted in DRC errors where pins are too close, I would just set all pin clearances to 0, you can rely on the net settings for DRC check.  You can double click on a pin and a pin properties dialog box should appear, under the "General" tab you can change the pins clearance.  If you select all the pins, when you change one pin the other will change as well.

[Tom__Sedlack]

I would recommend finding the closest spacing of any package in your design and setting the spacing to that value -1.  Setting it to 0 may not catch traces that inadvertantly cross when moving other lines.