I have completed several dense designs in Multisim/Ultiboad, using FPGAs of 1000+ balls. I found that the size of the design was not the issue, but the density caused usability problems. Specifically, my design called for 200+ controlled impedance diff pairs with a total board thickness of .062. Many of these pairs are used for multi GHz serial data channels. This led to very fine trace widths and spacings. Virtually all the automatic drawing aids worked either poorly or not at all. The autorouter did not work for even the uncritical single ended nets, so I wound up hand routing the entire design. This took several months of concentrated effort, and was far more tedious that I would have liked. The tight physical spacing requirements made it very difficult to escape the fine pitch (1mm) BGA with diff pairs using the "place bus" function, which bacame particularly time consuming. However, in the end the design was producable and worked well.
While Multisim seems to so down porportionally with design size, I had no trouble with Ultiboard's response times. I did the entire design on a normal laptop (2.2GHz dual core, 4GB RAM). My experience was that the Multisim schematic entry got a bit slow, but not objectionally so. In multisim, by far the most tedious task was to build the FPGA part. The inability of Multisim to read in the manufacturer's pin defnition files (.csv) is a major drawback to it's use in designs that require large devices.
In conclusion, I was able to successfully design a very dense high performance board with a 1000+ ball part, but this was a long and tedious experience. I would definitely think twice before doing it again. In my opinion, it would not take much improvement in Ultiboard to cut the time I spent on the layout in half - but until this is done high density layout will be a painful process.
Matt Stettler, Lawrence Berkeley National Laboratory
