JFET Question/Problems

[lacy]

I do not know if I am loosing my mind or if I may have found a problem with the JFET Simulation. I have included the simple circuit for someone to look at and let me know if I am completely crazy.

My understanding of JFETs is that a N_Channel JFET requires a positive going signal to decrease the channel resistance and therefore increase the output current. This would result in a voltage decrease at the drain. The opposite occurs when the input voltage is negative.going. The circuit I have attached seems to be doing something weird and doesn't seem to be following what I have outlined above.

Could some take a peek at it and see if it is just me or if there is a problem here with the way the JFETS are working. My theory is that the models for the JFETS are somehow screwed up and confirmation of this would let all of us know for sure.

Here is the circuit:

[lacy]

O.K. I thought I would reply to my own question here. I did some more experimenting and researching. I found that I am loosing my mind. The problem with my circuit is that the JFET is not properly biased. This is apparently why it is acting the way it is. To bias these things there has to be a source resistance in place to make the source more positve with respect to the gate. Then the signal can take this negative gate bias up or down.

I was experimenting with another users circuit when I confused myself. I guess it doesn't pay to experiment with electronics when you are tired as the mind doesn't think very clearly under these circumstances.

If anyone has a different take on this I am still willing to hear what you have to say.